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Searched refs:rd32 (Results 1 – 25 of 78) sorted by relevance

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/Linux-v5.4/drivers/net/ethernet/intel/igc/
Digc_mac.c27 ctrl = rd32(IGC_CTRL); in igc_disable_pcie_master()
32 if (!(rd32(IGC_STATUS) & in igc_disable_pcie_master()
181 ctrl = rd32(IGC_CTRL); in igc_force_mac_fc()
237 rd32(IGC_CRCERRS); in igc_clear_hw_cntrs_base()
238 rd32(IGC_SYMERRS); in igc_clear_hw_cntrs_base()
239 rd32(IGC_MPC); in igc_clear_hw_cntrs_base()
240 rd32(IGC_SCC); in igc_clear_hw_cntrs_base()
241 rd32(IGC_ECOL); in igc_clear_hw_cntrs_base()
242 rd32(IGC_MCC); in igc_clear_hw_cntrs_base()
243 rd32(IGC_LATECOL); in igc_clear_hw_cntrs_base()
[all …]
Digc_base.c40 ctrl = rd32(IGC_CTRL); in igc_reset_hw_base()
56 rd32(IGC_ICR); in igc_reset_hw_base()
68 u32 eecd = rd32(IGC_EECD); in igc_init_nvm_params_base()
113 ctrl = rd32(IGC_CTRL); in igc_setup_copper_link_base()
170 hw->bus.func = (rd32(IGC_STATUS) & IGC_STATUS_FUNC_MASK) >> in igc_init_phy_params_base()
342 rfctl = rd32(IGC_RFCTL); in igc_rx_fifo_flush_base()
346 if (!(rd32(IGC_MANC) & IGC_MANC_RCV_TCO_EN)) in igc_rx_fifo_flush_base()
351 rxdctl[i] = rd32(IGC_RXDCTL(i)); in igc_rx_fifo_flush_base()
360 rx_enabled |= rd32(IGC_RXDCTL(i)); in igc_rx_fifo_flush_base()
374 rlpml = rd32(IGC_RLPML); in igc_rx_fifo_flush_base()
[all …]
Digc_nvm.c23 reg = rd32(IGC_EERD); in igc_poll_eerd_eewr_done()
25 reg = rd32(IGC_EEWR); in igc_poll_eerd_eewr_done()
49 u32 eecd = rd32(IGC_EECD); in igc_acquire_nvm()
53 eecd = rd32(IGC_EECD); in igc_acquire_nvm()
59 eecd = rd32(IGC_EECD); in igc_acquire_nvm()
83 eecd = rd32(IGC_EECD); in igc_release_nvm()
122 data[i] = (rd32(IGC_EERD) >> IGC_NVM_RW_REG_DATA); in igc_read_nvm_eerd()
139 rar_high = rd32(IGC_RAH(0)); in igc_read_mac_addr()
140 rar_low = rd32(IGC_RAL(0)); in igc_read_mac_addr()
Digc_ethtool.c159 regs_buff[0] = rd32(IGC_CTRL); in igc_get_regs()
160 regs_buff[1] = rd32(IGC_STATUS); in igc_get_regs()
161 regs_buff[2] = rd32(IGC_CTRL_EXT); in igc_get_regs()
162 regs_buff[3] = rd32(IGC_MDIC); in igc_get_regs()
163 regs_buff[4] = rd32(IGC_CONNSW); in igc_get_regs()
166 regs_buff[5] = rd32(IGC_EECD); in igc_get_regs()
172 regs_buff[6] = rd32(IGC_EICS); in igc_get_regs()
173 regs_buff[7] = rd32(IGC_EICS); in igc_get_regs()
174 regs_buff[8] = rd32(IGC_EIMS); in igc_get_regs()
175 regs_buff[9] = rd32(IGC_EIMC); in igc_get_regs()
[all …]
Digc_i225.c48 swsm = rd32(IGC_SWSM); in igc_get_hw_semaphore_i225()
64 swsm = rd32(IGC_SWSM); in igc_get_hw_semaphore_i225()
81 swsm = rd32(IGC_SWSM); in igc_get_hw_semaphore_i225()
85 if (rd32(IGC_SWSM) & IGC_SWSM_SWESMBI) in igc_get_hw_semaphore_i225()
123 swfw_sync = rd32(IGC_SW_FW_SYNC); in igc_acquire_swfw_sync_i225()
162 swfw_sync = rd32(IGC_SW_FW_SYNC); in igc_release_swfw_sync_i225()
245 rd32(IGC_SRWR)) { in igc_write_nvm_srwr()
350 reg = rd32(IGC_EECD); in igc_pool_flash_update_done_i225()
376 flup = rd32(IGC_EECD) | IGC_EECD_FLUPD_I225; in igc_update_flash_i225()
457 eec = rd32(IGC_EECD); in igc_get_flash_presence_i225()
Digc_main.c154 ctrl_ext = rd32(IGC_CTRL_EXT); in igc_release_hw_control()
173 ctrl_ext = rd32(IGC_CTRL_EXT); in igc_get_hw_control()
674 rxcsum = rd32(IGC_RXCSUM); in igc_setup_mrqc()
711 rctl = rd32(IGC_RCTL); in igc_setup_rctl()
762 tctl = rd32(IGC_TCTL); in igc_setup_tctl()
1811 !(rd32(IGC_STATUS) & IGC_STATUS_TXOFF)) { in igc_clean_tx_irq()
1826 rd32(IGC_TDH(tx_ring->reg_idx)), in igc_clean_tx_irq()
1888 rd32(IGC_ICR); in igc_up()
1927 u32 rqdpc = rd32(IGC_RQDPC(i)); in igc_update_stats()
1967 adapter->stats.crcerrs += rd32(IGC_CRCERRS); in igc_update_stats()
[all …]
Digc_regs.h230 #define rd32(reg) (igc_rd32(hw, reg)) macro
232 #define wrfl() ((void)rd32(IGC_STATUS))
/Linux-v5.4/drivers/net/ethernet/intel/igb/
De1000_mac.c58 reg = rd32(E1000_STATUS); in igb_get_bus_info_pcie()
153 bits = rd32(E1000_VLVF(regindex)) & E1000_VLVF_VLANID_MASK; in igb_find_vlvf_slot()
223 bits = rd32(E1000_VLVF(vlvf_index)); in igb_vfta_set()
528 rd32(E1000_CRCERRS); in igb_clear_hw_cntrs_base()
529 rd32(E1000_SYMERRS); in igb_clear_hw_cntrs_base()
530 rd32(E1000_MPC); in igb_clear_hw_cntrs_base()
531 rd32(E1000_SCC); in igb_clear_hw_cntrs_base()
532 rd32(E1000_ECOL); in igb_clear_hw_cntrs_base()
533 rd32(E1000_MCC); in igb_clear_hw_cntrs_base()
534 rd32(E1000_LATECOL); in igb_clear_hw_cntrs_base()
[all …]
De1000_82575.c96 reg = rd32(E1000_MDIC); in igb_sgmii_uses_mdio_82575()
104 reg = rd32(E1000_MDICNFG); in igb_sgmii_uses_mdio_82575()
192 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_init_phy_params_82575()
225 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> in igb_init_phy_params_82575()
330 u32 eecd = rd32(E1000_EECD); in igb_init_nvm_params_82575()
453 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) in igb_init_mac_params_82575()
502 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_set_sfp_media_type_82575()
627 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_get_invariants_82575()
855 mdic = rd32(E1000_MDIC); in igb_get_phy_id_82575()
864 mdic = rd32(E1000_MDICNFG); in igb_get_phy_id_82575()
[all …]
Digb_ethtool.c146 status = rd32(E1000_STATUS); in igb_get_link_ksettings()
468 regs_buff[0] = rd32(E1000_CTRL); in igb_get_regs()
469 regs_buff[1] = rd32(E1000_STATUS); in igb_get_regs()
470 regs_buff[2] = rd32(E1000_CTRL_EXT); in igb_get_regs()
471 regs_buff[3] = rd32(E1000_MDIC); in igb_get_regs()
472 regs_buff[4] = rd32(E1000_SCTL); in igb_get_regs()
473 regs_buff[5] = rd32(E1000_CONNSW); in igb_get_regs()
474 regs_buff[6] = rd32(E1000_VET); in igb_get_regs()
475 regs_buff[7] = rd32(E1000_LEDCTL); in igb_get_regs()
476 regs_buff[8] = rd32(E1000_PBA); in igb_get_regs()
[all …]
Digb_ptp.c81 lo = rd32(E1000_SYSTIML); in igb_ptp_read_82576()
82 hi = rd32(E1000_SYSTIMH); in igb_ptp_read_82576()
102 rd32(E1000_SYSTIMR); in igb_ptp_read_82580()
103 lo = rd32(E1000_SYSTIML); in igb_ptp_read_82580()
104 hi = rd32(E1000_SYSTIMH); in igb_ptp_read_82580()
123 rd32(E1000_SYSTIMR); in igb_ptp_read_i210()
124 nsec = rd32(E1000_SYSTIML); in igb_ptp_read_i210()
125 sec = rd32(E1000_SYSTIMH); in igb_ptp_read_i210()
294 lo = rd32(E1000_SYSTIML); in igb_ptp_gettimex_82576()
296 hi = rd32(E1000_SYSTIMH); in igb_ptp_gettimex_82576()
[all …]
De1000_i210.c30 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
46 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
63 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
67 if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI) in igb_get_hw_semaphore_i210()
131 swfw_sync = rd32(E1000_SW_FW_SYNC); in igb_acquire_swfw_sync_i210()
170 swfw_sync = rd32(E1000_SW_FW_SYNC); in igb_release_swfw_sync_i210()
254 rd32(E1000_SRWR)) { in igb_write_nvm_srwr()
332 invm_dword = rd32(E1000_INVM_DATA_REG(i)); in igb_read_invm_word_i210()
457 invm_dword = rd32(E1000_INVM_DATA_REG(i)); in igb_read_invm_version()
633 reg = rd32(E1000_EECD); in igb_pool_flash_update_done_i210()
[all …]
Digb_main.c301 regs[n] = rd32(E1000_RDLEN(n)); in igb_regdump()
305 regs[n] = rd32(E1000_RDH(n)); in igb_regdump()
309 regs[n] = rd32(E1000_RDT(n)); in igb_regdump()
313 regs[n] = rd32(E1000_RXDCTL(n)); in igb_regdump()
317 regs[n] = rd32(E1000_RDBAL(n)); in igb_regdump()
321 regs[n] = rd32(E1000_RDBAH(n)); in igb_regdump()
325 regs[n] = rd32(E1000_RDBAL(n)); in igb_regdump()
329 regs[n] = rd32(E1000_TDBAH(n)); in igb_regdump()
333 regs[n] = rd32(E1000_TDLEN(n)); in igb_regdump()
337 regs[n] = rd32(E1000_TDH(n)); in igb_regdump()
[all …]
De1000_nvm.c53 u32 eecd = rd32(E1000_EECD); in igb_shift_out_eec_bits()
98 eecd = rd32(E1000_EECD); in igb_shift_in_eec_bits()
107 eecd = rd32(E1000_EECD); in igb_shift_in_eec_bits()
135 reg = rd32(E1000_EERD); in igb_poll_eerd_eewr_done()
137 reg = rd32(E1000_EEWR); in igb_poll_eerd_eewr_done()
160 u32 eecd = rd32(E1000_EECD); in igb_acquire_nvm()
166 eecd = rd32(E1000_EECD); in igb_acquire_nvm()
172 eecd = rd32(E1000_EECD); in igb_acquire_nvm()
195 u32 eecd = rd32(E1000_EECD); in igb_standby_nvm()
220 eecd = rd32(E1000_EECD); in e1000_stop_nvm()
[all …]
De1000_mbx.c243 u32 mbvficr = rd32(E1000_MBVFICR); in igb_check_for_bit_pf()
301 u32 vflre = rd32(E1000_VFLRE); in igb_check_for_rst_pf()
331 p2v_mailbox = rd32(E1000_P2VMAILBOX(vf_number)); in igb_obtain_mbx_lock_pf()
354 p2v_mailbox = rd32(E1000_P2VMAILBOX(vf_number)); in igb_release_mbx_lock_pf()
/Linux-v5.4/drivers/net/fjes/
Dfjes_ethtool.c194 regs_buff[0] = rd32(XSCT_OWNER_EPID); in fjes_get_regs()
195 regs_buff[1] = rd32(XSCT_MAX_EP); in fjes_get_regs()
198 regs_buff[4] = rd32(XSCT_DCTL); in fjes_get_regs()
201 regs_buff[8] = rd32(XSCT_CR); in fjes_get_regs()
202 regs_buff[9] = rd32(XSCT_CS); in fjes_get_regs()
203 regs_buff[10] = rd32(XSCT_SHSTSAL); in fjes_get_regs()
204 regs_buff[11] = rd32(XSCT_SHSTSAH); in fjes_get_regs()
206 regs_buff[13] = rd32(XSCT_REQBL); in fjes_get_regs()
207 regs_buff[14] = rd32(XSCT_REQBAL); in fjes_get_regs()
208 regs_buff[15] = rd32(XSCT_REQBAH); in fjes_get_regs()
[all …]
/Linux-v5.4/drivers/net/ethernet/intel/i40e/
Di40e_ptp.c46 lo = rd32(hw, I40E_PRTTSYN_TIME_L); in i40e_ptp_read()
48 hi = rd32(hw, I40E_PRTTSYN_TIME_H); in i40e_ptp_read()
236 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); in i40e_ptp_get_rx_events()
296 rd32(hw, I40E_PRTTSYN_RXTIME_H(i)); in i40e_ptp_rx_hang()
377 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L); in i40e_ptp_tx_hwtstamp()
378 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H); in i40e_ptp_tx_hwtstamp()
436 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index)); in i40e_ptp_rx_hwtstamp()
437 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index)); in i40e_ptp_rx_hwtstamp()
611 rd32(hw, I40E_PRTTSYN_STAT_0); in i40e_ptp_set_timestamp_mode()
612 rd32(hw, I40E_PRTTSYN_TXTIME_H); in i40e_ptp_set_timestamp_mode()
[all …]
Di40e_diag.c22 orig_val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
26 val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
36 val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
Di40e_adminq.c285 reg = rd32(hw, hw->aq.asq.bal); in i40e_config_asq_regs()
317 reg = rd32(hw, hw->aq.arq.bal); in i40e_config_arq_regs()
679 while (rd32(hw, hw->aq.asq.head) != ntc) { in i40e_clean_asq()
681 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); in i40e_clean_asq()
715 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; in i40e_asq_done()
755 val = rd32(hw, hw->aq.asq.head); in i40e_asq_send_command()
902 if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) { in i40e_asq_send_command()
971 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK; in i40e_clean_arq_element()
Di40e_lan_hmc.c106 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX); in i40e_init_lan_hmc()
109 size_exp = rd32(hw, I40E_GLHMC_LANTXOBJSZ); in i40e_init_lan_hmc()
126 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX); in i40e_init_lan_hmc()
132 size_exp = rd32(hw, I40E_GLHMC_LANRXOBJSZ); in i40e_init_lan_hmc()
149 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEMAX); in i40e_init_lan_hmc()
155 size_exp = rd32(hw, I40E_GLHMC_FCOEDDPOBJSZ); in i40e_init_lan_hmc()
172 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEFMAX); in i40e_init_lan_hmc()
178 size_exp = rd32(hw, I40E_GLHMC_FCOEFOBJSZ); in i40e_init_lan_hmc()
/Linux-v5.4/drivers/gpu/drm/nouveau/nvkm/core/
Dgpuobj.c76 .rd32 = nvkm_gpuobj_rd32_fast,
84 .rd32 = nvkm_gpuobj_heap_rd32,
139 .rd32 = nvkm_gpuobj_rd32_fast,
147 .rd32 = nvkm_gpuobj_rd32,
/Linux-v5.4/drivers/net/ethernet/intel/ice/
Dice_osdep.h14 #define rd32(a, reg) readl((a)->hw_addr + (reg)) macro
18 #define ice_flush(a) rd32((a), GLGEN_STAT)
Dice_controlq.c63 return (rd32(hw, cq->sq.len) & (cq->sq.len_mask | in ice_check_sq_alive()
266 if (rd32(hw, ring->bal) != lower_32_bits(ring->desc_buf.pa)) in ice_cfg_cq_regs()
795 while (rd32(hw, cq->sq.head) != ntc) { in ice_clean_sq()
797 "ntc %d head %d.\n", ntc, rd32(hw, cq->sq.head)); in ice_clean_sq()
825 return rd32(hw, cq->sq.head) == cq->sq.next_to_use; in ice_sq_done()
887 val = rd32(hw, cq->sq.head); in ice_sq_send_cmd()
1061 ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask); in ice_clean_rq_elem()
1118 ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask); in ice_clean_rq_elem()
/Linux-v5.4/drivers/net/ethernet/intel/iavf/
Diavf_adminq.c272 reg = rd32(hw, hw->aq.asq.bal); in iavf_config_asq_regs()
304 reg = rd32(hw, hw->aq.arq.bal); in iavf_config_arq_regs()
581 while (rd32(hw, hw->aq.asq.head) != ntc) { in iavf_clean_asq()
583 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); in iavf_clean_asq()
618 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; in iavf_asq_done()
657 val = rd32(hw, hw->aq.asq.head); in iavf_asq_send_command()
804 if (rd32(hw, hw->aq.asq.len) & IAVF_VF_ATQLEN1_ATQCRIT_MASK) { in iavf_asq_send_command()
872 ntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK; in iavf_clean_arq_element()
/Linux-v5.4/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
Dnv4c.c28 .rd32 = nv40_pci_rd32,

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