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/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_rlc.c39 if (adev->gfx.rlc.in_safe_mode) in amdgpu_gfx_rlc_enter_safe_mode()
43 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
49 adev->gfx.rlc.funcs->set_safe_mode(adev); in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.in_safe_mode = true; in amdgpu_gfx_rlc_enter_safe_mode()
63 if (!(adev->gfx.rlc.in_safe_mode)) in amdgpu_gfx_rlc_exit_safe_mode()
67 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
73 adev->gfx.rlc.funcs->unset_safe_mode(adev); in amdgpu_gfx_rlc_exit_safe_mode()
74 adev->gfx.rlc.in_safe_mode = false; in amdgpu_gfx_rlc_exit_safe_mode()
97 &adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_init_sr()
98 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_init_sr()
[all …]
Damdgpu_gfx.c42 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
43 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
44 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
53 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_bit_to_mec_queue()
54 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_gfx_bit_to_mec_queue()
55 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_gfx_bit_to_mec_queue()
56 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_gfx_bit_to_mec_queue()
57 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_gfx_bit_to_mec_queue()
65 adev->gfx.mec.queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
73 bit += me * adev->gfx.me.num_pipe_per_me in amdgpu_gfx_me_queue_to_bit()
[all …]
Dgfx_v9_0.c800 adev->gfx.scratch.num_reg = 8; in gfx_v9_0_scratch_init()
801 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_scratch_init()
802 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v9_0_scratch_init()
934 release_firmware(adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
935 adev->gfx.pfp_fw = NULL; in gfx_v9_0_free_microcode()
936 release_firmware(adev->gfx.me_fw); in gfx_v9_0_free_microcode()
937 adev->gfx.me_fw = NULL; in gfx_v9_0_free_microcode()
938 release_firmware(adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
939 adev->gfx.ce_fw = NULL; in gfx_v9_0_free_microcode()
940 release_firmware(adev->gfx.rlc_fw); in gfx_v9_0_free_microcode()
[all …]
Dgfx_v10_0.c358 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
395 adev->gfx.scratch.num_reg = 8; in gfx_v10_0_scratch_init()
396 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v10_0_scratch_init()
397 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v10_0_scratch_init()
551 release_firmware(adev->gfx.pfp_fw); in gfx_v10_0_free_microcode()
552 adev->gfx.pfp_fw = NULL; in gfx_v10_0_free_microcode()
553 release_firmware(adev->gfx.me_fw); in gfx_v10_0_free_microcode()
554 adev->gfx.me_fw = NULL; in gfx_v10_0_free_microcode()
555 release_firmware(adev->gfx.ce_fw); in gfx_v10_0_free_microcode()
556 adev->gfx.ce_fw = NULL; in gfx_v10_0_free_microcode()
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Dgfx_v6_0.c341 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
344 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v6_0_init_microcode()
347 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_init_microcode()
348 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
349 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
352 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
355 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v6_0_init_microcode()
358 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_init_microcode()
359 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
360 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
[all …]
Dgfx_v7_0.c930 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
933 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
938 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
941 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
946 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
949 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
954 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
957 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
963 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
966 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()
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Dgfx_v8_0.c831 adev->gfx.scratch.num_reg = 8; in gfx_v8_0_scratch_init()
832 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v8_0_scratch_init()
833 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v8_0_scratch_init()
931 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
932 adev->gfx.pfp_fw = NULL; in gfx_v8_0_free_microcode()
933 release_firmware(adev->gfx.me_fw); in gfx_v8_0_free_microcode()
934 adev->gfx.me_fw = NULL; in gfx_v8_0_free_microcode()
935 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
936 adev->gfx.ce_fw = NULL; in gfx_v8_0_free_microcode()
937 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
[all …]
Damdgpu_kms.c226 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
227 fw_info->feature = adev->gfx.me_feature_version; in amdgpu_firmware_info()
230 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
231 fw_info->feature = adev->gfx.pfp_feature_version; in amdgpu_firmware_info()
234 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
235 fw_info->feature = adev->gfx.ce_feature_version; in amdgpu_firmware_info()
238 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
239 fw_info->feature = adev->gfx.rlc_feature_version; in amdgpu_firmware_info()
242 fw_info->ver = adev->gfx.rlc_srlc_fw_version; in amdgpu_firmware_info()
243 fw_info->feature = adev->gfx.rlc_srlc_feature_version; in amdgpu_firmware_info()
[all …]
Damdgpu_discovery.c395 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se); in amdgpu_discovery_get_gfx_info()
396 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) + in amdgpu_discovery_get_gfx_info()
398 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
399 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
400 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c); in amdgpu_discovery_get_gfx_info()
401 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs); in amdgpu_discovery_get_gfx_info()
402 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds); in amdgpu_discovery_get_gfx_info()
403 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth); in amdgpu_discovery_get_gfx_info()
404 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth); in amdgpu_discovery_get_gfx_info()
405 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer); in amdgpu_discovery_get_gfx_info()
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Damdgpu_debugfs.c148 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
149 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) in amdgpu_debugfs_process_reg_op()
486 config[no_regs++] = adev->gfx.config.max_shader_engines; in amdgpu_debugfs_gca_config_read()
487 config[no_regs++] = adev->gfx.config.max_tile_pipes; in amdgpu_debugfs_gca_config_read()
488 config[no_regs++] = adev->gfx.config.max_cu_per_sh; in amdgpu_debugfs_gca_config_read()
489 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
490 config[no_regs++] = adev->gfx.config.max_backends_per_se; in amdgpu_debugfs_gca_config_read()
491 config[no_regs++] = adev->gfx.config.max_texture_channel_caches; in amdgpu_debugfs_gca_config_read()
492 config[no_regs++] = adev->gfx.config.max_gprs; in amdgpu_debugfs_gca_config_read()
493 config[no_regs++] = adev->gfx.config.max_gs_threads; in amdgpu_debugfs_gca_config_read()
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Damdgpu_amdkfd.c151 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, in amdgpu_amdkfd_device_init()
152 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, in amdgpu_amdkfd_device_init()
165 adev->gfx.mec.queue_bitmap, in amdgpu_amdkfd_device_init()
169 if (adev->gfx.kiq.ring.sched.ready) in amdgpu_amdkfd_device_init()
171 adev->gfx.kiq.ring.me - 1, in amdgpu_amdkfd_device_init()
172 adev->gfx.kiq.ring.pipe, in amdgpu_amdkfd_device_init()
173 adev->gfx.kiq.ring.queue), in amdgpu_amdkfd_device_init()
180 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
181 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
392 return adev->gfx.pfp_fw_version; in amdgpu_amdkfd_get_fw_version()
[all …]
Damdgpu_atomfirmware.c443 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines; in amdgpu_atomfirmware_get_gfx_info()
444 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
445 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
446 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()
447 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches; in amdgpu_atomfirmware_get_gfx_info()
448 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); in amdgpu_atomfirmware_get_gfx_info()
449 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; in amdgpu_atomfirmware_get_gfx_info()
450 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth; in amdgpu_atomfirmware_get_gfx_info()
451 adev->gfx.config.gs_prim_buffer_depth = in amdgpu_atomfirmware_get_gfx_info()
453 adev->gfx.config.double_offchip_lds_buf = in amdgpu_atomfirmware_get_gfx_info()
[all …]
Damdgpu_ucode.c396 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
397 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
398 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
399 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
400 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
401 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
402 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
403 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
404 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
511 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; in amdgpu_ucode_init_single_fw()
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Damdgpu_amdkfd_gfx_v9.c71 config->gb_addr_config = adev->gfx.config.gb_addr_config; in kgd_gfx_v9_get_tile_config()
73 config->tile_config_ptr = adev->gfx.config.tile_mode_array; in kgd_gfx_v9_get_tile_config()
75 ARRAY_SIZE(adev->gfx.config.tile_mode_array); in kgd_gfx_v9_get_tile_config()
77 adev->gfx.config.macrotile_mode_array; in kgd_gfx_v9_get_tile_config()
79 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in kgd_gfx_v9_get_tile_config()
111 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
112 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
120 unsigned int bit = (pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
215 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_init_interrupts()
216 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_init_interrupts()
[all …]
Damdgpu_amdkfd_gfx_v10.c118 config->gb_addr_config = adev->gfx.config.gb_addr_config; in amdgpu_amdkfd_get_tile_config()
125 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, in amdgpu_amdkfd_get_tile_config()
127 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, in amdgpu_amdkfd_get_tile_config()
131 config->tile_config_ptr = adev->gfx.config.tile_mode_array; in amdgpu_amdkfd_get_tile_config()
133 ARRAY_SIZE(adev->gfx.config.tile_mode_array); in amdgpu_amdkfd_get_tile_config()
135 adev->gfx.config.macrotile_mode_array; in amdgpu_amdkfd_get_tile_config()
137 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in amdgpu_amdkfd_get_tile_config()
200 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
201 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
209 unsigned int bit = (pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
[all …]
Damdgpu_amdkfd_gfx_v8.c111 config->gb_addr_config = adev->gfx.config.gb_addr_config; in get_tile_config()
112 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, in get_tile_config()
114 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, in get_tile_config()
117 config->tile_config_ptr = adev->gfx.config.tile_mode_array; in get_tile_config()
119 ARRAY_SIZE(adev->gfx.config.tile_mode_array); in get_tile_config()
121 adev->gfx.config.macrotile_mode_array; in get_tile_config()
123 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in get_tile_config()
188 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
189 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
250 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_init_interrupts()
[all …]
Damdgpu_amdkfd_gfx_v7.c156 config->gb_addr_config = adev->gfx.config.gb_addr_config; in get_tile_config()
157 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, in get_tile_config()
159 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, in get_tile_config()
162 config->tile_config_ptr = adev->gfx.config.tile_mode_array; in get_tile_config()
164 ARRAY_SIZE(adev->gfx.config.tile_mode_array); in get_tile_config()
166 adev->gfx.config.macrotile_mode_array; in get_tile_config()
168 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in get_tile_config()
232 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
233 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
293 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_init_interrupts()
[all …]
Damdgpu_cgs.c173 fw_version = adev->gfx.ce_fw_version; in amdgpu_get_firmware_version()
176 fw_version = adev->gfx.pfp_fw_version; in amdgpu_get_firmware_version()
179 fw_version = adev->gfx.me_fw_version; in amdgpu_get_firmware_version()
182 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
185 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
188 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
191 fw_version = adev->gfx.rlc_fw_version; in amdgpu_get_firmware_version()
Dvcn_v1_0.c336 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
338 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
340 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
342 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
344 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
346 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
348 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
350 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
352 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
354 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
[all …]
Damdgpu_device.c1472 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); in amdgpu_device_parse_gpu_info_fw()
1473 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); in amdgpu_device_parse_gpu_info_fw()
1474 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); in amdgpu_device_parse_gpu_info_fw()
1475 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); in amdgpu_device_parse_gpu_info_fw()
1476 adev->gfx.config.max_texture_channel_caches = in amdgpu_device_parse_gpu_info_fw()
1478 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); in amdgpu_device_parse_gpu_info_fw()
1479 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); in amdgpu_device_parse_gpu_info_fw()
1480 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); in amdgpu_device_parse_gpu_info_fw()
1481 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); in amdgpu_device_parse_gpu_info_fw()
1482 adev->gfx.config.double_offchip_lds_buf = in amdgpu_device_parse_gpu_info_fw()
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/gpu/
Daspeed-gfx.txt6 + aspeed,ast2500-gfx
7 + aspeed,ast2400-gfx
26 gfx: display@1e6e6000 {
27 compatible = "aspeed,ast2500-gfx", "syscon";
/Linux-v5.4/Documentation/devicetree/bindings/mfd/
Daspeed-gfx.txt8 - compatible: "aspeed,ast2500-gfx", "syscon"
14 gfx: display@1e6e6000 {
15 compatible = "aspeed,ast2500-gfx", "syscon";
/Linux-v5.4/arch/arm/boot/dts/
Daspeed-bmc-intel-s2600wf.dts114 &gfx {
119 aspeed,external-nodes = <&gfx &lhc>;
Daspeed-bmc-inspur-on5263m5.dts119 &gfx {
124 aspeed,external-nodes = <&gfx &lhc>;
Daspeed-bmc-arm-centriq2400-rep.dts210 &gfx {
215 aspeed,external-nodes = <&gfx &lhc>;

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