Lines Matching refs:gfx
831 adev->gfx.scratch.num_reg = 8; in gfx_v8_0_scratch_init()
832 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v8_0_scratch_init()
833 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v8_0_scratch_init()
931 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
932 adev->gfx.pfp_fw = NULL; in gfx_v8_0_free_microcode()
933 release_firmware(adev->gfx.me_fw); in gfx_v8_0_free_microcode()
934 adev->gfx.me_fw = NULL; in gfx_v8_0_free_microcode()
935 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
936 adev->gfx.ce_fw = NULL; in gfx_v8_0_free_microcode()
937 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
938 adev->gfx.rlc_fw = NULL; in gfx_v8_0_free_microcode()
939 release_firmware(adev->gfx.mec_fw); in gfx_v8_0_free_microcode()
940 adev->gfx.mec_fw = NULL; in gfx_v8_0_free_microcode()
943 release_firmware(adev->gfx.mec2_fw); in gfx_v8_0_free_microcode()
944 adev->gfx.mec2_fw = NULL; in gfx_v8_0_free_microcode()
946 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
996 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
999 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1003 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1007 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v8_0_init_microcode()
1010 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v8_0_init_microcode()
1011 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1012 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1016 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1019 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1023 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1027 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v8_0_init_microcode()
1030 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v8_0_init_microcode()
1031 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1033 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1037 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1040 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1044 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1048 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v8_0_init_microcode()
1051 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v8_0_init_microcode()
1052 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1053 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1059 if (adev->gfx.ce_feature_version >= 46 && in gfx_v8_0_init_microcode()
1060 adev->gfx.pfp_feature_version >= 46) { in gfx_v8_0_init_microcode()
1067 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1070 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); in gfx_v8_0_init_microcode()
1071 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v8_0_init_microcode()
1072 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1073 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1075 adev->gfx.rlc.save_and_restore_offset = in gfx_v8_0_init_microcode()
1077 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v8_0_init_microcode()
1079 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v8_0_init_microcode()
1081 adev->gfx.rlc.reg_restore_list_size = in gfx_v8_0_init_microcode()
1083 adev->gfx.rlc.reg_list_format_start = in gfx_v8_0_init_microcode()
1085 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v8_0_init_microcode()
1087 adev->gfx.rlc.starting_offsets_start = in gfx_v8_0_init_microcode()
1089 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v8_0_init_microcode()
1091 adev->gfx.rlc.reg_list_size_bytes = in gfx_v8_0_init_microcode()
1094 adev->gfx.rlc.register_list_format = in gfx_v8_0_init_microcode()
1095 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + in gfx_v8_0_init_microcode()
1096 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); in gfx_v8_0_init_microcode()
1098 if (!adev->gfx.rlc.register_list_format) { in gfx_v8_0_init_microcode()
1105 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) in gfx_v8_0_init_microcode()
1106 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); in gfx_v8_0_init_microcode()
1108 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v8_0_init_microcode()
1112 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) in gfx_v8_0_init_microcode()
1113 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); in gfx_v8_0_init_microcode()
1117 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1120 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1124 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1128 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v8_0_init_microcode()
1131 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v8_0_init_microcode()
1132 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1133 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1139 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1142 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1146 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1149 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v8_0_init_microcode()
1153 adev->gfx.mec2_fw->data; in gfx_v8_0_init_microcode()
1154 adev->gfx.mec2_fw_version = in gfx_v8_0_init_microcode()
1156 adev->gfx.mec2_feature_version = in gfx_v8_0_init_microcode()
1160 adev->gfx.mec2_fw = NULL; in gfx_v8_0_init_microcode()
1166 info->fw = adev->gfx.pfp_fw; in gfx_v8_0_init_microcode()
1173 info->fw = adev->gfx.me_fw; in gfx_v8_0_init_microcode()
1180 info->fw = adev->gfx.ce_fw; in gfx_v8_0_init_microcode()
1187 info->fw = adev->gfx.rlc_fw; in gfx_v8_0_init_microcode()
1194 info->fw = adev->gfx.mec_fw; in gfx_v8_0_init_microcode()
1200 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v8_0_init_microcode()
1207 info->fw = adev->gfx.mec_fw; in gfx_v8_0_init_microcode()
1212 if (adev->gfx.mec2_fw) { in gfx_v8_0_init_microcode()
1215 info->fw = adev->gfx.mec2_fw; in gfx_v8_0_init_microcode()
1226 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_init_microcode()
1227 adev->gfx.pfp_fw = NULL; in gfx_v8_0_init_microcode()
1228 release_firmware(adev->gfx.me_fw); in gfx_v8_0_init_microcode()
1229 adev->gfx.me_fw = NULL; in gfx_v8_0_init_microcode()
1230 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_init_microcode()
1231 adev->gfx.ce_fw = NULL; in gfx_v8_0_init_microcode()
1232 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_init_microcode()
1233 adev->gfx.rlc_fw = NULL; in gfx_v8_0_init_microcode()
1234 release_firmware(adev->gfx.mec_fw); in gfx_v8_0_init_microcode()
1235 adev->gfx.mec_fw = NULL; in gfx_v8_0_init_microcode()
1236 release_firmware(adev->gfx.mec2_fw); in gfx_v8_0_init_microcode()
1237 adev->gfx.mec2_fw = NULL; in gfx_v8_0_init_microcode()
1249 if (adev->gfx.rlc.cs_data == NULL) in gfx_v8_0_get_csb_buffer()
1261 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v8_0_get_csb_buffer()
1279 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); in gfx_v8_0_get_csb_buffer()
1280 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v8_0_get_csb_buffer()
1302 adev->gfx.rlc.cs_data = vi_cs_data; in gfx_v8_0_rlc_init()
1304 cs_data = adev->gfx.rlc.cs_data; in gfx_v8_0_rlc_init()
1315 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ in gfx_v8_0_rlc_init()
1328 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); in gfx_v8_0_csb_vram_pin()
1332 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, in gfx_v8_0_csb_vram_pin()
1335 adev->gfx.rlc.clear_state_gpu_addr = in gfx_v8_0_csb_vram_pin()
1336 amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj); in gfx_v8_0_csb_vram_pin()
1338 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v8_0_csb_vram_pin()
1347 if (!adev->gfx.rlc.clear_state_obj) in gfx_v8_0_csb_vram_unpin()
1350 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); in gfx_v8_0_csb_vram_unpin()
1352 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); in gfx_v8_0_csb_vram_unpin()
1353 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v8_0_csb_vram_unpin()
1359 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v8_0_mec_fini()
1368 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v8_0_mec_init()
1373 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE; in gfx_v8_0_mec_init()
1377 &adev->gfx.mec.hpd_eop_obj, in gfx_v8_0_mec_init()
1378 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v8_0_mec_init()
1387 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_init()
1388 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_init()
1549 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; in gfx_v8_0_do_edc_gpr_workarounds()
1720 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1721 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1722 adev->gfx.config.max_cu_per_sh = 6; in gfx_v8_0_gpu_early_init()
1723 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1724 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1725 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1726 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1727 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1728 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1730 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1731 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1732 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1733 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1737 adev->gfx.config.max_shader_engines = 4; in gfx_v8_0_gpu_early_init()
1738 adev->gfx.config.max_tile_pipes = 16; in gfx_v8_0_gpu_early_init()
1739 adev->gfx.config.max_cu_per_sh = 16; in gfx_v8_0_gpu_early_init()
1740 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1741 adev->gfx.config.max_backends_per_se = 4; in gfx_v8_0_gpu_early_init()
1742 adev->gfx.config.max_texture_channel_caches = 16; in gfx_v8_0_gpu_early_init()
1743 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1744 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1745 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1747 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1748 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1749 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1750 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1758 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1759 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1760 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1762 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1763 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1764 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1765 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1773 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1774 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1775 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1777 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1778 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1779 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1780 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1784 adev->gfx.config.max_shader_engines = 4; in gfx_v8_0_gpu_early_init()
1785 adev->gfx.config.max_tile_pipes = 8; in gfx_v8_0_gpu_early_init()
1786 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()
1787 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1788 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1789 adev->gfx.config.max_texture_channel_caches = 8; in gfx_v8_0_gpu_early_init()
1790 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1791 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1792 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1794 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1795 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1796 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1797 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1801 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1802 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1803 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1804 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1805 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()
1806 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1807 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1808 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1809 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1811 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1812 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1813 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1814 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1818 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1819 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1820 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1821 adev->gfx.config.max_backends_per_se = 1; in gfx_v8_0_gpu_early_init()
1822 adev->gfx.config.max_cu_per_sh = 3; in gfx_v8_0_gpu_early_init()
1823 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1824 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1825 adev->gfx.config.max_gs_threads = 16; in gfx_v8_0_gpu_early_init()
1826 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1828 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1829 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1830 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1831 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1835 adev->gfx.config.max_shader_engines = 2; in gfx_v8_0_gpu_early_init()
1836 adev->gfx.config.max_tile_pipes = 4; in gfx_v8_0_gpu_early_init()
1837 adev->gfx.config.max_cu_per_sh = 2; in gfx_v8_0_gpu_early_init()
1838 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1839 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1840 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v8_0_gpu_early_init()
1841 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1842 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1843 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1845 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1846 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1847 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1848 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1854 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v8_0_gpu_early_init()
1855 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; in gfx_v8_0_gpu_early_init()
1857 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v8_0_gpu_early_init()
1858 adev->gfx.config.mem_max_burst_length_bytes = 256; in gfx_v8_0_gpu_early_init()
1882 adev->gfx.config.mem_row_size_in_kb = 2; in gfx_v8_0_gpu_early_init()
1884 adev->gfx.config.mem_row_size_in_kb = 1; in gfx_v8_0_gpu_early_init()
1887 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in gfx_v8_0_gpu_early_init()
1888 if (adev->gfx.config.mem_row_size_in_kb > 4) in gfx_v8_0_gpu_early_init()
1889 adev->gfx.config.mem_row_size_in_kb = 4; in gfx_v8_0_gpu_early_init()
1892 adev->gfx.config.shader_engine_tile_size = 32; in gfx_v8_0_gpu_early_init()
1893 adev->gfx.config.num_gpus = 1; in gfx_v8_0_gpu_early_init()
1894 adev->gfx.config.multi_gpu_tile_size = 64; in gfx_v8_0_gpu_early_init()
1897 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v8_0_gpu_early_init()
1909 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v8_0_gpu_early_init()
1919 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v8_0_compute_ring_init()
1921 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v8_0_compute_ring_init()
1931 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v8_0_compute_ring_init()
1936 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v8_0_compute_ring_init()
1941 &adev->gfx.eop_irq, irq_type); in gfx_v8_0_compute_ring_init()
1966 adev->gfx.mec.num_mec = 2; in gfx_v8_0_sw_init()
1971 adev->gfx.mec.num_mec = 1; in gfx_v8_0_sw_init()
1975 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v8_0_sw_init()
1976 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v8_0_sw_init()
1979 …q_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq); in gfx_v8_0_sw_init()
1985 &adev->gfx.priv_reg_irq); in gfx_v8_0_sw_init()
1991 &adev->gfx.priv_inst_irq); in gfx_v8_0_sw_init()
1997 &adev->gfx.cp_ecc_error_irq); in gfx_v8_0_sw_init()
2003 &adev->gfx.sq_irq); in gfx_v8_0_sw_init()
2009 INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func); in gfx_v8_0_sw_init()
2011 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v8_0_sw_init()
2021 r = adev->gfx.rlc.funcs->init(adev); in gfx_v8_0_sw_init()
2034 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v8_0_sw_init()
2035 ring = &adev->gfx.gfx_ring[i]; in gfx_v8_0_sw_init()
2044 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, in gfx_v8_0_sw_init()
2053 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v8_0_sw_init()
2054 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v8_0_sw_init()
2055 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v8_0_sw_init()
2076 kiq = &adev->gfx.kiq; in gfx_v8_0_sw_init()
2086 adev->gfx.ce_ram_size = 0x8000; in gfx_v8_0_sw_init()
2100 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_sw_fini()
2101 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v8_0_sw_fini()
2102 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_sw_fini()
2103 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v8_0_sw_fini()
2106 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); in gfx_v8_0_sw_fini()
2111 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v8_0_sw_fini()
2112 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_sw_fini()
2113 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v8_0_sw_fini()
2116 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v8_0_sw_fini()
2117 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v8_0_sw_fini()
2118 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v8_0_sw_fini()
2128 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v8_0_tiling_mode_table_init()
2129 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in gfx_v8_0_tiling_mode_table_init()
2132 modearray = adev->gfx.config.tile_mode_array; in gfx_v8_0_tiling_mode_table_init()
2133 mod2array = adev->gfx.config.macrotile_mode_array; in gfx_v8_0_tiling_mode_table_init()
3486 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v8_0_get_rb_active_bitmap()
3487 adev->gfx.config.max_sh_per_se); in gfx_v8_0_get_rb_active_bitmap()
3538 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v8_0_write_harvested_raster_configs()
3539 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v8_0_write_harvested_raster_configs()
3648 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v8_0_setup_rb()
3649 adev->gfx.config.max_sh_per_se; in gfx_v8_0_setup_rb()
3653 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_setup_rb()
3654 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3657 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v8_0_setup_rb()
3663 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v8_0_setup_rb()
3664 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v8_0_setup_rb()
3666 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v8_0_setup_rb()
3667 adev->gfx.config.max_shader_engines, 16); in gfx_v8_0_setup_rb()
3671 if (!adev->gfx.config.backend_enable_mask || in gfx_v8_0_setup_rb()
3672 adev->gfx.config.num_rbs >= num_rb_pipes) { in gfx_v8_0_setup_rb()
3677 adev->gfx.config.backend_enable_mask, in gfx_v8_0_setup_rb()
3682 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_setup_rb()
3683 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3685 adev->gfx.config.rb_config[i][j].rb_backend_disable = in gfx_v8_0_setup_rb()
3687 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = in gfx_v8_0_setup_rb()
3689 adev->gfx.config.rb_config[i][j].raster_config = in gfx_v8_0_setup_rb()
3691 adev->gfx.config.rb_config[i][j].raster_config_1 = in gfx_v8_0_setup_rb()
3775 adev->gfx.config.double_offchip_lds_buf = 1; in gfx_v8_0_config_init()
3779 adev->gfx.config.double_offchip_lds_buf = 0; in gfx_v8_0_config_init()
3790 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_constants_init()
3791 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_constants_init()
3792 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); in gfx_v8_0_constants_init()
3847 (adev->gfx.config.sc_prim_fifo_size_frontend << in gfx_v8_0_constants_init()
3849 (adev->gfx.config.sc_prim_fifo_size_backend << in gfx_v8_0_constants_init()
3851 (adev->gfx.config.sc_hiz_tile_fifo_size << in gfx_v8_0_constants_init()
3853 (adev->gfx.config.sc_earlyz_tile_fifo_size << in gfx_v8_0_constants_init()
3873 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_wait_for_rlc_serdes()
3874 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_wait_for_rlc_serdes()
3922 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v8_0_init_csb()
3924 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v8_0_init_csb()
3926 adev->gfx.rlc.clear_state_size); in gfx_v8_0_init_csb()
3989 kmemdup(adev->gfx.rlc.register_list_format, in gfx_v8_0_init_save_restore_list()
3990 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); in gfx_v8_0_init_save_restore_list()
3996 adev->gfx.rlc.reg_list_format_size_bytes >> 2, in gfx_v8_0_init_save_restore_list()
4008 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
4009 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]); in gfx_v8_0_init_save_restore_list()
4012 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start); in gfx_v8_0_init_save_restore_list()
4013 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
4016 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; in gfx_v8_0_init_save_restore_list()
4018 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size); in gfx_v8_0_init_save_restore_list()
4023 adev->gfx.rlc.starting_offsets_start); in gfx_v8_0_init_save_restore_list()
4088 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v8_0_init_pg()
4090 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); in gfx_v8_0_init_pg()
4137 adev->gfx.rlc.funcs->stop(adev); in gfx_v8_0_rlc_resume()
4138 adev->gfx.rlc.funcs->reset(adev); in gfx_v8_0_rlc_resume()
4140 adev->gfx.rlc.funcs->start(adev); in gfx_v8_0_rlc_resume()
4158 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_cp_gfx_enable()
4159 adev->gfx.gfx_ring[i].sched.ready = false; in gfx_v8_0_cp_gfx_enable()
4196 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_start()
4202 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v8_0_cp_gfx_start()
4238 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); in gfx_v8_0_cp_gfx_start()
4239 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v8_0_cp_gfx_start()
4305 ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_resume()
4353 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_cp_compute_enable()
4354 adev->gfx.compute_ring[i].sched.ready = false; in gfx_v8_0_cp_compute_enable()
4355 adev->gfx.kiq.ring.sched.ready = false; in gfx_v8_0_cp_compute_enable()
4377 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v8_0_kiq_kcq_enable()
4382 if (!test_bit(i, adev->gfx.mec.queue_bitmap)) in gfx_v8_0_kiq_kcq_enable()
4396 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8); in gfx_v8_0_kiq_kcq_enable()
4410 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kiq_kcq_enable()
4411 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kiq_kcq_enable()
4647 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kiq_init_queue()
4648 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kiq_init_queue()
4669 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kiq_init_queue()
4670 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kiq_init_queue()
4680 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v8_0_kcq_init_queue()
4692 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kcq_init_queue()
4693 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kcq_init_queue()
4696 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kcq_init_queue()
4697 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kcq_init_queue()
4722 ring = &adev->gfx.kiq.ring; in gfx_v8_0_kiq_resume()
4747 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_resume()
4748 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kcq_resume()
4780 ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_test_all_rings()
4785 ring = &adev->gfx.kiq.ring; in gfx_v8_0_cp_test_all_rings()
4790 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_cp_test_all_rings()
4791 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_cp_test_all_rings()
4844 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v8_0_hw_init()
4856 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v8_0_kcq_disable()
4858 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings); in gfx_v8_0_kcq_disable()
4862 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_disable()
4863 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kcq_disable()
4936 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v8_0_hw_fini()
4937 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v8_0_hw_fini()
4939 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v8_0_hw_fini()
4941 amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0); in gfx_v8_0_hw_fini()
4956 adev->gfx.rlc.funcs->stop(adev); in gfx_v8_0_hw_fini()
5028 adev->gfx.grbm_soft_reset = grbm_soft_reset; in gfx_v8_0_check_soft_reset()
5029 adev->gfx.srbm_soft_reset = srbm_soft_reset; in gfx_v8_0_check_soft_reset()
5032 adev->gfx.grbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
5033 adev->gfx.srbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
5043 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_pre_soft_reset()
5044 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_pre_soft_reset()
5047 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_pre_soft_reset()
5050 adev->gfx.rlc.funcs->stop(adev); in gfx_v8_0_pre_soft_reset()
5063 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_pre_soft_reset()
5064 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_pre_soft_reset()
5085 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_soft_reset()
5086 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_soft_reset()
5089 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_soft_reset()
5090 srbm_soft_reset = adev->gfx.srbm_soft_reset; in gfx_v8_0_soft_reset()
5146 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_post_soft_reset()
5147 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_post_soft_reset()
5150 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_post_soft_reset()
5158 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_post_soft_reset()
5159 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_post_soft_reset()
5177 adev->gfx.rlc.funcs->start(adev); in gfx_v8_0_post_soft_reset()
5194 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v8_0_get_gpu_clock_counter()
5198 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v8_0_get_gpu_clock_counter()
5312 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; in gfx_v8_0_early_init()
5313 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; in gfx_v8_0_early_init()
5314 adev->gfx.funcs = &gfx_v8_0_gfx_funcs; in gfx_v8_0_early_init()
5328 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v8_0_late_init()
5332 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v8_0_late_init()
5341 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v8_0_late_init()
5347 r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0); in gfx_v8_0_late_init()
6266 pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe; in gfx_v8_0_ring_set_pipe_percent()
6286 mutex_lock(&adev->gfx.pipe_reserve_mutex); in gfx_v8_0_pipe_reserve_resources()
6289 set_bit(pipe, adev->gfx.pipe_reserve_bitmap); in gfx_v8_0_pipe_reserve_resources()
6291 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap); in gfx_v8_0_pipe_reserve_resources()
6293 if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) { in gfx_v8_0_pipe_reserve_resources()
6295 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) in gfx_v8_0_pipe_reserve_resources()
6296 gfx_v8_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i], in gfx_v8_0_pipe_reserve_resources()
6299 for (i = 0; i < adev->gfx.num_compute_rings; ++i) in gfx_v8_0_pipe_reserve_resources()
6300 gfx_v8_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i], in gfx_v8_0_pipe_reserve_resources()
6304 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) { in gfx_v8_0_pipe_reserve_resources()
6305 iring = &adev->gfx.gfx_ring[i]; in gfx_v8_0_pipe_reserve_resources()
6310 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); in gfx_v8_0_pipe_reserve_resources()
6314 for (i = 0; i < adev->gfx.num_compute_rings; ++i) { in gfx_v8_0_pipe_reserve_resources()
6315 iring = &adev->gfx.compute_ring[i]; in gfx_v8_0_pipe_reserve_resources()
6320 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); in gfx_v8_0_pipe_reserve_resources()
6325 mutex_unlock(&adev->gfx.pipe_reserve_mutex); in gfx_v8_0_pipe_reserve_resources()
6726 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v8_0_eop_irq()
6730 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_eop_irq()
6731 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_eop_irq()
6756 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); in gfx_v8_0_fault()
6760 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_fault()
6761 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_fault()
6869 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.sq_work.work); in gfx_v8_0_sq_irq_work_func()
6886 if (work_pending(&adev->gfx.sq_work.work)) { in gfx_v8_0_sq_irq()
6889 adev->gfx.sq_work.ih_data = ih_data; in gfx_v8_0_sq_irq()
6890 schedule_work(&adev->gfx.sq_work.work); in gfx_v8_0_sq_irq()
7020 adev->gfx.kiq.ring.funcs = &gfx_v8_0_ring_funcs_kiq; in gfx_v8_0_set_ring_funcs()
7022 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_set_ring_funcs()
7023 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx; in gfx_v8_0_set_ring_funcs()
7025 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_set_ring_funcs()
7026 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute; in gfx_v8_0_set_ring_funcs()
7056 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v8_0_set_irq_funcs()
7057 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; in gfx_v8_0_set_irq_funcs()
7059 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7060 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; in gfx_v8_0_set_irq_funcs()
7062 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7063 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs; in gfx_v8_0_set_irq_funcs()
7065 adev->gfx.cp_ecc_error_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7066 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs; in gfx_v8_0_set_irq_funcs()
7068 adev->gfx.sq_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7069 adev->gfx.sq_irq.funcs = &gfx_v8_0_sq_irq_funcs; in gfx_v8_0_set_irq_funcs()
7074 adev->gfx.rlc.funcs = &iceland_rlc_funcs; in gfx_v8_0_set_rlc_funcs()
7107 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v8_0_get_cu_active_bitmap()
7116 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v8_0_get_cu_info()
7125 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v8_0_get_cu_info()
7130 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_get_cu_info()
7131 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_get_cu_info()
7142 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v8_0_get_cu_info()