Lines Matching refs:gfx
358 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
395 adev->gfx.scratch.num_reg = 8; in gfx_v10_0_scratch_init()
396 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v10_0_scratch_init()
397 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v10_0_scratch_init()
551 release_firmware(adev->gfx.pfp_fw); in gfx_v10_0_free_microcode()
552 adev->gfx.pfp_fw = NULL; in gfx_v10_0_free_microcode()
553 release_firmware(adev->gfx.me_fw); in gfx_v10_0_free_microcode()
554 adev->gfx.me_fw = NULL; in gfx_v10_0_free_microcode()
555 release_firmware(adev->gfx.ce_fw); in gfx_v10_0_free_microcode()
556 adev->gfx.ce_fw = NULL; in gfx_v10_0_free_microcode()
557 release_firmware(adev->gfx.rlc_fw); in gfx_v10_0_free_microcode()
558 adev->gfx.rlc_fw = NULL; in gfx_v10_0_free_microcode()
559 release_firmware(adev->gfx.mec_fw); in gfx_v10_0_free_microcode()
560 adev->gfx.mec_fw = NULL; in gfx_v10_0_free_microcode()
561 release_firmware(adev->gfx.mec2_fw); in gfx_v10_0_free_microcode()
562 adev->gfx.mec2_fw = NULL; in gfx_v10_0_free_microcode()
564 kfree(adev->gfx.rlc.register_list_format); in gfx_v10_0_free_microcode()
569 adev->gfx.cp_fw_write_wait = false; in gfx_v10_0_check_fw_write_wait()
575 if ((adev->gfx.me_fw_version >= 0x00000046) && in gfx_v10_0_check_fw_write_wait()
576 (adev->gfx.me_feature_version >= 27) && in gfx_v10_0_check_fw_write_wait()
577 (adev->gfx.pfp_fw_version >= 0x00000068) && in gfx_v10_0_check_fw_write_wait()
578 (adev->gfx.pfp_feature_version >= 27) && in gfx_v10_0_check_fw_write_wait()
579 (adev->gfx.mec_fw_version >= 0x0000005b) && in gfx_v10_0_check_fw_write_wait()
580 (adev->gfx.mec_feature_version >= 27)) in gfx_v10_0_check_fw_write_wait()
581 adev->gfx.cp_fw_write_wait = true; in gfx_v10_0_check_fw_write_wait()
587 if (adev->gfx.cp_fw_write_wait == false) in gfx_v10_0_check_fw_write_wait()
597 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; in gfx_v10_0_init_rlc_ext_microcode()
598 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); in gfx_v10_0_init_rlc_ext_microcode()
599 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); in gfx_v10_0_init_rlc_ext_microcode()
600 …adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size… in gfx_v10_0_init_rlc_ext_microcode()
601 …adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl… in gfx_v10_0_init_rlc_ext_microcode()
602 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); in gfx_v10_0_init_rlc_ext_microcode()
603 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); in gfx_v10_0_init_rlc_ext_microcode()
604 …adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_b… in gfx_v10_0_init_rlc_ext_microcode()
605 …adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_o… in gfx_v10_0_init_rlc_ext_microcode()
606 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); in gfx_v10_0_init_rlc_ext_microcode()
607 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); in gfx_v10_0_init_rlc_ext_microcode()
608 …adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_b… in gfx_v10_0_init_rlc_ext_microcode()
609 …adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_o… in gfx_v10_0_init_rlc_ext_microcode()
610 adev->gfx.rlc.reg_list_format_direct_reg_list_length = in gfx_v10_0_init_rlc_ext_microcode()
661 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v10_0_init_microcode()
664 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v10_0_init_microcode()
667 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v10_0_init_microcode()
668 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v10_0_init_microcode()
669 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v10_0_init_microcode()
672 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v10_0_init_microcode()
675 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v10_0_init_microcode()
678 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v10_0_init_microcode()
679 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v10_0_init_microcode()
680 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v10_0_init_microcode()
683 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v10_0_init_microcode()
686 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v10_0_init_microcode()
689 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v10_0_init_microcode()
690 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v10_0_init_microcode()
691 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v10_0_init_microcode()
694 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); in gfx_v10_0_init_microcode()
697 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); in gfx_v10_0_init_microcode()
698 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v10_0_init_microcode()
702 adev->gfx.rlc.is_rlc_v2_1 = true; in gfx_v10_0_init_microcode()
704 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v10_0_init_microcode()
705 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v10_0_init_microcode()
706 adev->gfx.rlc.save_and_restore_offset = in gfx_v10_0_init_microcode()
708 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v10_0_init_microcode()
710 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v10_0_init_microcode()
712 adev->gfx.rlc.reg_restore_list_size = in gfx_v10_0_init_microcode()
714 adev->gfx.rlc.reg_list_format_start = in gfx_v10_0_init_microcode()
716 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v10_0_init_microcode()
718 adev->gfx.rlc.starting_offsets_start = in gfx_v10_0_init_microcode()
720 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v10_0_init_microcode()
722 adev->gfx.rlc.reg_list_size_bytes = in gfx_v10_0_init_microcode()
724 adev->gfx.rlc.register_list_format = in gfx_v10_0_init_microcode()
725 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + in gfx_v10_0_init_microcode()
726 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); in gfx_v10_0_init_microcode()
727 if (!adev->gfx.rlc.register_list_format) { in gfx_v10_0_init_microcode()
735 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); in gfx_v10_0_init_microcode()
737 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v10_0_init_microcode()
742 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); in gfx_v10_0_init_microcode()
744 if (adev->gfx.rlc.is_rlc_v2_1) in gfx_v10_0_init_microcode()
748 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v10_0_init_microcode()
751 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v10_0_init_microcode()
754 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v10_0_init_microcode()
755 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v10_0_init_microcode()
756 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v10_0_init_microcode()
759 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v10_0_init_microcode()
761 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v10_0_init_microcode()
765 adev->gfx.mec2_fw->data; in gfx_v10_0_init_microcode()
766 adev->gfx.mec2_fw_version = in gfx_v10_0_init_microcode()
768 adev->gfx.mec2_feature_version = in gfx_v10_0_init_microcode()
772 adev->gfx.mec2_fw = NULL; in gfx_v10_0_init_microcode()
778 info->fw = adev->gfx.pfp_fw; in gfx_v10_0_init_microcode()
785 info->fw = adev->gfx.me_fw; in gfx_v10_0_init_microcode()
792 info->fw = adev->gfx.ce_fw; in gfx_v10_0_init_microcode()
799 info->fw = adev->gfx.rlc_fw; in gfx_v10_0_init_microcode()
804 if (adev->gfx.rlc.is_rlc_v2_1 && in gfx_v10_0_init_microcode()
805 adev->gfx.rlc.save_restore_list_cntl_size_bytes && in gfx_v10_0_init_microcode()
806 adev->gfx.rlc.save_restore_list_gpm_size_bytes && in gfx_v10_0_init_microcode()
807 adev->gfx.rlc.save_restore_list_srm_size_bytes) { in gfx_v10_0_init_microcode()
810 info->fw = adev->gfx.rlc_fw; in gfx_v10_0_init_microcode()
812 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); in gfx_v10_0_init_microcode()
816 info->fw = adev->gfx.rlc_fw; in gfx_v10_0_init_microcode()
818 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); in gfx_v10_0_init_microcode()
822 info->fw = adev->gfx.rlc_fw; in gfx_v10_0_init_microcode()
824 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); in gfx_v10_0_init_microcode()
829 info->fw = adev->gfx.mec_fw; in gfx_v10_0_init_microcode()
838 info->fw = adev->gfx.mec_fw; in gfx_v10_0_init_microcode()
842 if (adev->gfx.mec2_fw) { in gfx_v10_0_init_microcode()
845 info->fw = adev->gfx.mec2_fw; in gfx_v10_0_init_microcode()
854 info->fw = adev->gfx.mec2_fw; in gfx_v10_0_init_microcode()
867 release_firmware(adev->gfx.pfp_fw); in gfx_v10_0_init_microcode()
868 adev->gfx.pfp_fw = NULL; in gfx_v10_0_init_microcode()
869 release_firmware(adev->gfx.me_fw); in gfx_v10_0_init_microcode()
870 adev->gfx.me_fw = NULL; in gfx_v10_0_init_microcode()
871 release_firmware(adev->gfx.ce_fw); in gfx_v10_0_init_microcode()
872 adev->gfx.ce_fw = NULL; in gfx_v10_0_init_microcode()
873 release_firmware(adev->gfx.rlc_fw); in gfx_v10_0_init_microcode()
874 adev->gfx.rlc_fw = NULL; in gfx_v10_0_init_microcode()
875 release_firmware(adev->gfx.mec_fw); in gfx_v10_0_init_microcode()
876 adev->gfx.mec_fw = NULL; in gfx_v10_0_init_microcode()
877 release_firmware(adev->gfx.mec2_fw); in gfx_v10_0_init_microcode()
878 adev->gfx.mec2_fw = NULL; in gfx_v10_0_init_microcode()
924 if (adev->gfx.rlc.cs_data == NULL) in gfx_v10_0_get_csb_buffer()
936 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v10_0_get_csb_buffer()
955 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); in gfx_v10_0_get_csb_buffer()
967 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v10_0_rlc_fini()
968 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v10_0_rlc_fini()
969 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v10_0_rlc_fini()
972 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v10_0_rlc_fini()
973 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v10_0_rlc_fini()
974 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v10_0_rlc_fini()
982 adev->gfx.rlc.cs_data = gfx10_cs_data; in gfx_v10_0_rlc_init()
984 cs_data = adev->gfx.rlc.cs_data; in gfx_v10_0_rlc_init()
1000 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); in gfx_v10_0_csb_vram_pin()
1004 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, in gfx_v10_0_csb_vram_pin()
1007 adev->gfx.rlc.clear_state_gpu_addr = in gfx_v10_0_csb_vram_pin()
1008 amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj); in gfx_v10_0_csb_vram_pin()
1010 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v10_0_csb_vram_pin()
1019 if (!adev->gfx.rlc.clear_state_obj) in gfx_v10_0_csb_vram_unpin()
1022 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); in gfx_v10_0_csb_vram_unpin()
1024 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); in gfx_v10_0_csb_vram_unpin()
1025 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v10_0_csb_vram_unpin()
1031 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v10_0_mec_fini()
1032 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v10_0_mec_fini()
1039 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); in gfx_v10_0_me_init()
1061 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v10_0_mec_init()
1065 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; in gfx_v10_0_mec_init()
1069 &adev->gfx.mec.hpd_eop_obj, in gfx_v10_0_mec_init()
1070 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v10_0_mec_init()
1078 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); in gfx_v10_0_mec_init()
1080 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v10_0_mec_init()
1081 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v10_0_mec_init()
1084 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v10_0_mec_init()
1086 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v10_0_mec_init()
1092 &adev->gfx.mec.mec_fw_obj, in gfx_v10_0_mec_init()
1093 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v10_0_mec_init()
1103 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v10_0_mec_init()
1104 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v10_0_mec_init()
1198 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; in gfx_v10_0_gpu_early_init()
1204 adev->gfx.config.max_hw_contexts = 8; in gfx_v10_0_gpu_early_init()
1205 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v10_0_gpu_early_init()
1206 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v10_0_gpu_early_init()
1207 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v10_0_gpu_early_init()
1208 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v10_0_gpu_early_init()
1216 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v10_0_gpu_early_init()
1218 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v10_0_gpu_early_init()
1219 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
1222 adev->gfx.config.max_tile_pipes = in gfx_v10_0_gpu_early_init()
1223 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v10_0_gpu_early_init()
1225 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v10_0_gpu_early_init()
1226 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
1228 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v10_0_gpu_early_init()
1229 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
1231 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v10_0_gpu_early_init()
1232 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
1234 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v10_0_gpu_early_init()
1235 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
1246 ring = &adev->gfx.gfx_ring[ring_id]; in gfx_v10_0_gfx_ring_init()
1263 &adev->gfx.eop_irq, irq_type); in gfx_v10_0_gfx_ring_init()
1274 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v10_0_compute_ring_init()
1276 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v10_0_compute_ring_init()
1286 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v10_0_compute_ring_init()
1291 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v10_0_compute_ring_init()
1296 &adev->gfx.eop_irq, irq_type); in gfx_v10_0_compute_ring_init()
1313 adev->gfx.me.num_me = 1; in gfx_v10_0_sw_init()
1314 adev->gfx.me.num_pipe_per_me = 2; in gfx_v10_0_sw_init()
1315 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v10_0_sw_init()
1316 adev->gfx.mec.num_mec = 2; in gfx_v10_0_sw_init()
1317 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v10_0_sw_init()
1318 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v10_0_sw_init()
1321 adev->gfx.me.num_me = 1; in gfx_v10_0_sw_init()
1322 adev->gfx.me.num_pipe_per_me = 1; in gfx_v10_0_sw_init()
1323 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v10_0_sw_init()
1324 adev->gfx.mec.num_mec = 1; in gfx_v10_0_sw_init()
1325 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v10_0_sw_init()
1326 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v10_0_sw_init()
1333 &adev->gfx.kiq.irq); in gfx_v10_0_sw_init()
1340 &adev->gfx.eop_irq); in gfx_v10_0_sw_init()
1346 &adev->gfx.priv_reg_irq); in gfx_v10_0_sw_init()
1352 &adev->gfx.priv_inst_irq); in gfx_v10_0_sw_init()
1356 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v10_0_sw_init()
1377 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v10_0_sw_init()
1378 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v10_0_sw_init()
1379 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v10_0_sw_init()
1394 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v10_0_sw_init()
1395 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v10_0_sw_init()
1396 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v10_0_sw_init()
1417 kiq = &adev->gfx.kiq; in gfx_v10_0_sw_init()
1433 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; in gfx_v10_0_sw_init()
1442 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, in gfx_v10_0_pfp_fini()
1443 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v10_0_pfp_fini()
1444 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v10_0_pfp_fini()
1449 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, in gfx_v10_0_ce_fini()
1450 &adev->gfx.ce.ce_fw_gpu_addr, in gfx_v10_0_ce_fini()
1451 (void **)&adev->gfx.ce.ce_fw_ptr); in gfx_v10_0_ce_fini()
1456 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, in gfx_v10_0_me_fini()
1457 &adev->gfx.me.me_fw_gpu_addr, in gfx_v10_0_me_fini()
1458 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v10_0_me_fini()
1466 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v10_0_sw_fini()
1467 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v10_0_sw_fini()
1468 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v10_0_sw_fini()
1469 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v10_0_sw_fini()
1472 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); in gfx_v10_0_sw_fini()
1532 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v10_0_get_rb_active_bitmap()
1533 adev->gfx.config.max_sh_per_se); in gfx_v10_0_get_rb_active_bitmap()
1543 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v10_0_setup_rb()
1544 adev->gfx.config.max_sh_per_se; in gfx_v10_0_setup_rb()
1547 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v10_0_setup_rb()
1548 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_setup_rb()
1551 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v10_0_setup_rb()
1558 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v10_0_setup_rb()
1559 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v10_0_setup_rb()
1572 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * in gfx_v10_0_init_pa_sc_tile_steering_override()
1573 adev->gfx.config.num_sc_per_sh; in gfx_v10_0_init_pa_sc_tile_steering_override()
1577 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; in gfx_v10_0_init_pa_sc_tile_steering_override()
1579 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; in gfx_v10_0_init_pa_sc_tile_steering_override()
1654 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; in gfx_v10_0_tcp_harvest()
1682 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v10_0_tcp_harvest()
1683 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_tcp_harvest()
1727 adev->gfx.config.tcc_disabled_mask = in gfx_v10_0_get_tcc_info()
1742 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); in gfx_v10_0_constants_init()
1744 adev->gfx.config.pa_sc_tile_steering_override = in gfx_v10_0_constants_init()
1792 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v10_0_init_csb()
1794 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v10_0_init_csb()
1795 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v10_0_init_csb()
1877 if (!adev->gfx.rlc_fw) in gfx_v10_0_rlc_load_microcode()
1880 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v10_0_rlc_load_microcode()
1883 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v10_0_rlc_load_microcode()
1894 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v10_0_rlc_load_microcode()
1916 adev->gfx.rlc.funcs->stop(adev); in gfx_v10_0_rlc_resume()
1937 adev->gfx.rlc.funcs->start(adev); in gfx_v10_0_rlc_resume()
1961 &adev->gfx.rlc.rlc_toc_bo, in gfx_v10_0_parse_rlc_toc()
1962 &adev->gfx.rlc.rlc_toc_gpu_addr, in gfx_v10_0_parse_rlc_toc()
1963 (void **)&adev->gfx.rlc.rlc_toc_buf); in gfx_v10_0_parse_rlc_toc()
1970 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); in gfx_v10_0_parse_rlc_toc()
1972 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; in gfx_v10_0_parse_rlc_toc()
2023 &adev->gfx.rlc.rlc_autoload_bo, in gfx_v10_0_rlc_backdoor_autoload_buffer_init()
2024 &adev->gfx.rlc.rlc_autoload_gpu_addr, in gfx_v10_0_rlc_backdoor_autoload_buffer_init()
2025 (void **)&adev->gfx.rlc.rlc_autoload_ptr); in gfx_v10_0_rlc_backdoor_autoload_buffer_init()
2036 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
2037 &adev->gfx.rlc.rlc_toc_gpu_addr, in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
2038 (void **)&adev->gfx.rlc.rlc_toc_buf); in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
2039 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
2040 &adev->gfx.rlc.rlc_autoload_gpu_addr, in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
2041 (void **)&adev->gfx.rlc.rlc_autoload_ptr); in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
2051 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; in gfx_v10_0_rlc_backdoor_autoload_copy_ucode()
2076 data = adev->gfx.rlc.rlc_toc_buf; in gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode()
2093 adev->gfx.pfp_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
2094 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
2103 adev->gfx.ce_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
2104 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
2113 adev->gfx.me_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
2114 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
2123 adev->gfx.rlc_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
2124 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
2133 adev->gfx.mec_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
2134 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
2190 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; in gfx_v10_0_rlc_backdoor_autoload_enable()
2239 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v10_0_rlc_backdoor_autoload_config_me_cache()
2276 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v10_0_rlc_backdoor_autoload_config_ce_cache()
2313 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache()
2350 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
2412 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v10_0_cp_gfx_enable()
2413 adev->gfx.gfx_ring[i].sched.ready = false; in gfx_v10_0_cp_gfx_enable()
2429 adev->gfx.pfp_fw->data; in gfx_v10_0_cp_gfx_load_pfp_microcode()
2433 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v10_0_cp_gfx_load_pfp_microcode()
2439 &adev->gfx.pfp.pfp_fw_obj, in gfx_v10_0_cp_gfx_load_pfp_microcode()
2440 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v10_0_cp_gfx_load_pfp_microcode()
2441 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v10_0_cp_gfx_load_pfp_microcode()
2448 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); in gfx_v10_0_cp_gfx_load_pfp_microcode()
2450 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); in gfx_v10_0_cp_gfx_load_pfp_microcode()
2451 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); in gfx_v10_0_cp_gfx_load_pfp_microcode()
2482 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); in gfx_v10_0_cp_gfx_load_pfp_microcode()
2484 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); in gfx_v10_0_cp_gfx_load_pfp_microcode()
2499 adev->gfx.ce_fw->data; in gfx_v10_0_cp_gfx_load_ce_microcode()
2503 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + in gfx_v10_0_cp_gfx_load_ce_microcode()
2509 &adev->gfx.ce.ce_fw_obj, in gfx_v10_0_cp_gfx_load_ce_microcode()
2510 &adev->gfx.ce.ce_fw_gpu_addr, in gfx_v10_0_cp_gfx_load_ce_microcode()
2511 (void **)&adev->gfx.ce.ce_fw_ptr); in gfx_v10_0_cp_gfx_load_ce_microcode()
2518 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); in gfx_v10_0_cp_gfx_load_ce_microcode()
2520 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); in gfx_v10_0_cp_gfx_load_ce_microcode()
2521 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); in gfx_v10_0_cp_gfx_load_ce_microcode()
2551 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); in gfx_v10_0_cp_gfx_load_ce_microcode()
2553 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); in gfx_v10_0_cp_gfx_load_ce_microcode()
2568 adev->gfx.me_fw->data; in gfx_v10_0_cp_gfx_load_me_microcode()
2572 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v10_0_cp_gfx_load_me_microcode()
2578 &adev->gfx.me.me_fw_obj, in gfx_v10_0_cp_gfx_load_me_microcode()
2579 &adev->gfx.me.me_fw_gpu_addr, in gfx_v10_0_cp_gfx_load_me_microcode()
2580 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v10_0_cp_gfx_load_me_microcode()
2587 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); in gfx_v10_0_cp_gfx_load_me_microcode()
2589 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); in gfx_v10_0_cp_gfx_load_me_microcode()
2590 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); in gfx_v10_0_cp_gfx_load_me_microcode()
2620 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); in gfx_v10_0_cp_gfx_load_me_microcode()
2622 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); in gfx_v10_0_cp_gfx_load_me_microcode()
2631 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v10_0_cp_gfx_load_microcode()
2667 adev->gfx.config.max_hw_contexts - 1); in gfx_v10_0_cp_gfx_start()
2672 ring = &adev->gfx.gfx_ring[0]; in gfx_v10_0_cp_gfx_start()
2704 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); in gfx_v10_0_cp_gfx_start()
2720 ring = &adev->gfx.gfx_ring[1]; in gfx_v10_0_cp_gfx_start()
2789 ring = &adev->gfx.gfx_ring[0]; in gfx_v10_0_cp_gfx_resume()
2830 ring = &adev->gfx.gfx_ring[1]; in gfx_v10_0_cp_gfx_resume()
2868 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v10_0_cp_gfx_resume()
2869 ring = &adev->gfx.gfx_ring[i]; in gfx_v10_0_cp_gfx_resume()
2886 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v10_0_cp_compute_enable()
2887 adev->gfx.compute_ring[i].sched.ready = false; in gfx_v10_0_cp_compute_enable()
2888 adev->gfx.kiq.ring.sched.ready = false; in gfx_v10_0_cp_compute_enable()
2901 if (!adev->gfx.mec_fw) in gfx_v10_0_cp_compute_load_microcode()
2906 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v10_0_cp_compute_load_microcode()
2910 (adev->gfx.mec_fw->data + in gfx_v10_0_cp_compute_load_microcode()
2941 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & in gfx_v10_0_cp_compute_load_microcode()
2944 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v10_0_cp_compute_load_microcode()
2953 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v10_0_cp_compute_load_microcode()
3128 if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]) in gfx_v10_0_gfx_init_queue()
3129 memcpy(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], mqd, sizeof(*mqd)); in gfx_v10_0_gfx_init_queue()
3132 if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]) in gfx_v10_0_gfx_init_queue()
3133 memcpy(mqd, adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd)); in gfx_v10_0_gfx_init_queue()
3154 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gfx_v10_0_kiq_enable_kgq()
3155 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v10_0_kiq_enable_kgq()
3162 adev->gfx.num_gfx_rings); in gfx_v10_0_kiq_enable_kgq()
3168 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v10_0_kiq_enable_kgq()
3169 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); in gfx_v10_0_kiq_enable_kgq()
3185 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v10_0_cp_async_gfx_ring_resume()
3186 ring = &adev->gfx.gfx_ring[i]; in gfx_v10_0_cp_async_gfx_ring_resume()
3211 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v10_0_cp_async_gfx_ring_resume()
3212 ring = &adev->gfx.gfx_ring[i]; in gfx_v10_0_cp_async_gfx_ring_resume()
3466 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v10_0_kiq_init_queue()
3467 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v10_0_kiq_init_queue()
3487 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v10_0_kiq_init_queue()
3488 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v10_0_kiq_init_queue()
3498 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v10_0_kcq_init_queue()
3508 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v10_0_kcq_init_queue()
3509 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v10_0_kcq_init_queue()
3512 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v10_0_kcq_init_queue()
3513 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v10_0_kcq_init_queue()
3530 ring = &adev->gfx.kiq.ring; in gfx_v10_0_kiq_resume()
3555 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_kcq_resume()
3556 ring = &adev->gfx.compute_ring[i]; in gfx_v10_0_kcq_resume()
3614 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v10_0_cp_resume()
3615 ring = &adev->gfx.gfx_ring[i]; in gfx_v10_0_cp_resume()
3625 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_cp_resume()
3626 ring = &adev->gfx.compute_ring[i]; in gfx_v10_0_cp_resume()
3785 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gfx_v10_0_kiq_disable_kgq()
3793 adev->gfx.num_gfx_rings)) in gfx_v10_0_kiq_disable_kgq()
3796 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v10_0_kiq_disable_kgq()
3797 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], in gfx_v10_0_kiq_disable_kgq()
3809 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v10_0_hw_fini()
3810 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v10_0_hw_fini()
3939 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v10_0_get_gpu_clock_counter()
3943 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v10_0_get_gpu_clock_counter()
3980 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS; in gfx_v10_0_early_init()
3981 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; in gfx_v10_0_early_init()
3997 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v10_0_late_init()
4001 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v10_0_late_init()
4251 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); in gfx_v10_0_set_powergating_state()
4644 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gfx_v10_0_ring_preempt_ib()
4803 fw_version_ok = adev->gfx.cp_fw_write_wait; in gfx_v10_0_ring_emit_reg_write_reg_wait()
4966 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v10_0_eop_irq()
4968 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); in gfx_v10_0_eop_irq()
4972 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_eop_irq()
4973 ring = &adev->gfx.compute_ring[i]; in gfx_v10_0_eop_irq()
5035 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v10_0_handle_priv_fault()
5036 ring = &adev->gfx.gfx_ring[i]; in gfx_v10_0_handle_priv_fault()
5044 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_handle_priv_fault()
5045 ring = &adev->gfx.compute_ring[i]; in gfx_v10_0_handle_priv_fault()
5080 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); in gfx_v10_0_kiq_set_interrupt_state()
5124 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); in gfx_v10_0_kiq_irq()
5275 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; in gfx_v10_0_set_ring_funcs()
5277 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v10_0_set_ring_funcs()
5278 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; in gfx_v10_0_set_ring_funcs()
5280 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v10_0_set_ring_funcs()
5281 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; in gfx_v10_0_set_ring_funcs()
5306 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v10_0_set_irq_funcs()
5307 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; in gfx_v10_0_set_irq_funcs()
5309 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; in gfx_v10_0_set_irq_funcs()
5310 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; in gfx_v10_0_set_irq_funcs()
5312 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v10_0_set_irq_funcs()
5313 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; in gfx_v10_0_set_irq_funcs()
5315 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v10_0_set_irq_funcs()
5316 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; in gfx_v10_0_set_irq_funcs()
5325 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; in gfx_v10_0_set_rlc_funcs()
5371 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); in gfx_v10_0_get_wgp_active_bitmap_per_sh()
5407 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v10_0_get_cu_info()
5408 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_get_cu_info()
5419 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v10_0_get_cu_info()
5421 if (counter < adev->gfx.config.max_cu_per_sh) in gfx_v10_0_get_cu_info()