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Searched refs:RREG32 (Results 1 – 25 of 146) sorted by relevance

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/Linux-v5.4/drivers/gpu/drm/radeon/
Dradeon_bios.c260 bus_cntl = RREG32(R600_BUS_CNTL); in ni_read_disabled_bios()
261 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); in ni_read_disabled_bios()
262 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); in ni_read_disabled_bios()
263 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); in ni_read_disabled_bios()
264 rom_cntl = RREG32(R600_ROM_CNTL); in ni_read_disabled_bios()
306 viph_control = RREG32(RADEON_VIPH_CONTROL); in r700_read_disabled_bios()
307 bus_cntl = RREG32(R600_BUS_CNTL); in r700_read_disabled_bios()
308 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); in r700_read_disabled_bios()
309 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); in r700_read_disabled_bios()
310 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); in r700_read_disabled_bios()
[all …]
Dradeon_legacy_encoders.c64 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_update()
92 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); in radeon_legacy_lvds_update()
95 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_update()
100 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_update()
195 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_mode_set()
198 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
205 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
216 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
286 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> in radeon_legacy_get_backlight_level()
360 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> in radeon_legacy_backlight_get_brightness()
[all …]
Dvce_v2_0.c43 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
47 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
51 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
57 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
62 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
67 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
77 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_dyn_cg()
87 orig = tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
93 orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
134 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v2_0_init_cg()
[all …]
Dradeon_i2c.c132 temp = RREG32(rec->mask_clk_reg); in pre_xfer()
138 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; in pre_xfer()
141 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; in pre_xfer()
145 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; in pre_xfer()
148 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; in pre_xfer()
152 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; in pre_xfer()
154 temp = RREG32(rec->mask_clk_reg); in pre_xfer()
156 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; in pre_xfer()
158 temp = RREG32(rec->mask_data_reg); in pre_xfer()
171 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; in post_xfer()
[all …]
Dvce_v1_0.c63 return RREG32(VCE_RB_RPTR); in vce_v1_0_get_rptr()
65 return RREG32(VCE_RB_RPTR2); in vce_v1_0_get_rptr()
80 return RREG32(VCE_RB_WPTR); in vce_v1_0_get_wptr()
82 return RREG32(VCE_RB_WPTR2); in vce_v1_0_get_wptr()
107 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
111 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
116 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
120 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
124 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
129 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
[all …]
Drs600.c63 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) in avivo_is_in_vblank()
73 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
74 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
97 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) in avivo_wait_for_vblank()
121 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
138 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
154 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
232 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
241 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
327 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_prepare()
[all …]
Drv730_dpm.c202 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
204 RREG32(CG_SPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
206 RREG32(CG_SPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
208 RREG32(CG_SPLL_SPREAD_SPECTRUM); in rv730_read_clock_registers()
210 RREG32(CG_SPLL_SPREAD_SPECTRUM_2); in rv730_read_clock_registers()
213 RREG32(TCI_MCLK_PWRMGT_CNTL); in rv730_read_clock_registers()
215 RREG32(TCI_DLL_CNTL); in rv730_read_clock_registers()
217 RREG32(CG_MPLL_FUNC_CNTL); in rv730_read_clock_registers()
219 RREG32(CG_MPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
221 RREG32(CG_MPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
[all …]
Dr600.c127 r = RREG32(R600_RCU_DATA); in r600_rcu_rreg()
149 r = RREG32(R600_UVD_CTX_DATA); in r600_uvd_ctx_rreg()
183 *val = RREG32(reg); in r600_get_allowed_info_register()
352 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> in rv6xx_get_temp()
797 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) in r600_gui_idle()
811 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
815 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
819 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
823 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
828 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
[all …]
Drs400.c158 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; in rs400_gart_enable()
162 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; in rs400_gart_enable()
249 tmp = RREG32(RADEON_MC_STATUS); in rs400_mc_wait_for_idle()
264 RREG32(RADEON_MC_STATUS)); in rs400_gpu_init()
278 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; in rs400_mc_init()
292 r = RREG32(RS480_NB_MC_DATA); in rs400_mc_rreg()
317 tmp = RREG32(RADEON_HOST_PATH_CNTL); in rs400_debugfs_gart_info()
319 tmp = RREG32(RADEON_BUS_CNTL); in rs400_debugfs_gart_info()
332 tmp = RREG32(RS690_HDP_FB_LOCATION); in rs400_debugfs_gart_info()
335 tmp = RREG32(RADEON_AGP_BASE); in rs400_debugfs_gart_info()
[all …]
Dr100.c80 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) in r100_is_in_vblank()
85 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) in r100_is_in_vblank()
97 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
98 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
100 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
101 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
125 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) in r100_wait_for_vblank()
128 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) in r100_wait_for_vblank()
174 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
200 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
[all …]
Dcik.c178 *val = RREG32(reg); in cik_get_allowed_info_register()
195 r = RREG32(CIK_DIDT_IND_DATA); in cik_didt_rreg()
257 (void)RREG32(PCIE_INDEX); in cik_pciep_rreg()
258 r = RREG32(PCIE_DATA); in cik_pciep_rreg()
269 (void)RREG32(PCIE_INDEX); in cik_pciep_wreg()
271 (void)RREG32(PCIE_DATA); in cik_pciep_wreg()
1915 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; in ci_mc_load_microcode()
1933 tmp = RREG32(MC_SEQ_MISC0); in ci_mc_load_microcode()
1956 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) in ci_mc_load_microcode()
1961 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) in ci_mc_load_microcode()
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgmc_v8_0.c184 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_stop()
202 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_resume()
328 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_tonga_mc_load_microcode()
351 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
357 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
397 data = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_polaris_mc_load_microcode()
421 data = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_polaris_mc_load_microcode()
436 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v8_0_vram_gtt_location()
471 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v8_0_mc_program()
476 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v8_0_mc_program()
[all …]
Dgmc_v7_0.c96 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_stop()
114 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_resume()
203 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
226 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
232 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
245 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v7_0_vram_gtt_location()
280 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v7_0_mc_program()
285 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v7_0_mc_program()
305 tmp = RREG32(mmHDP_MISC_CNTL); in gmc_v7_0_mc_program()
309 tmp = RREG32(mmHDP_HOST_PATH_CNTL); in gmc_v7_0_mc_program()
[all …]
Damdgpu_i2c.c51 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_pre_xfer()
57 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; in amdgpu_i2c_pre_xfer()
60 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; in amdgpu_i2c_pre_xfer()
64 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; in amdgpu_i2c_pre_xfer()
67 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; in amdgpu_i2c_pre_xfer()
71 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; in amdgpu_i2c_pre_xfer()
73 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_pre_xfer()
75 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; in amdgpu_i2c_pre_xfer()
77 temp = RREG32(rec->mask_data_reg); in amdgpu_i2c_pre_xfer()
90 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; in amdgpu_i2c_post_xfer()
[all …]
Dvce_v2_0.c60 return RREG32(mmVCE_RB_RPTR); in vce_v2_0_ring_get_rptr()
62 return RREG32(mmVCE_RB_RPTR2); in vce_v2_0_ring_get_rptr()
77 return RREG32(mmVCE_RB_WPTR); in vce_v2_0_ring_get_wptr()
79 return RREG32(mmVCE_RB_WPTR2); in vce_v2_0_ring_get_wptr()
105 uint32_t status = RREG32(mmVCE_LMI_STATUS); in vce_v2_0_lmi_clean()
122 uint32_t status = RREG32(mmVCE_STATUS); in vce_v2_0_firmware_loaded()
151 tmp = RREG32(mmVCE_CLOCK_GATING_A); in vce_v2_0_init_cg()
157 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_init_cg()
162 tmp = RREG32(mmVCE_CLOCK_GATING_B); in vce_v2_0_init_cg()
208 return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK); in vce_v2_0_is_idle()
[all …]
Dgmc_v6_0.c81 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v6_0_mc_stop()
100 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v6_0_mc_resume()
138 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) in gmc_v6_0_init_microcode()
185 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; in gmc_v6_0_mc_load_microcode()
210 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK) in gmc_v6_0_mc_load_microcode()
215 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK) in gmc_v6_0_mc_load_microcode()
228 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v6_0_vram_gtt_location()
257 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v6_0_mc_program()
262 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v6_0_mc_program()
289 tmp = RREG32(mmMC_ARB_RAMCFG); in gmc_v6_0_mc_init()
[all …]
Dcz_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_enable_interrupts()
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_disable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_disable_interrupts()
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in cz_ih_irq_init()
148 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_irq_init()
205 tmp = RREG32(mmIH_RB_CNTL); in cz_ih_get_wptr()
334 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_is_idle()
350 tmp = RREG32(mmSRBM_STATUS); in cz_ih_wait_for_idle()
362 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_soft_reset()
[all …]
Diceland_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_enable_interrupts()
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_disable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_disable_interrupts()
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in iceland_ih_irq_init()
148 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_irq_init()
205 tmp = RREG32(mmIH_RB_CNTL); in iceland_ih_get_wptr()
334 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_is_idle()
350 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_wait_for_idle()
362 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_soft_reset()
[all …]
Dcik_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_enable_interrupts()
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_disable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_disable_interrupts()
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in cik_ih_irq_init()
203 tmp = RREG32(mmIH_RB_CNTL); in cik_ih_get_wptr()
355 u32 tmp = RREG32(mmSRBM_STATUS); in cik_ih_is_idle()
371 tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK; in cik_ih_wait_for_idle()
384 u32 tmp = RREG32(mmSRBM_STATUS); in cik_ih_soft_reset()
390 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_ih_soft_reset()
[all …]
Dsi_ih.c35 u32 ih_cntl = RREG32(IH_CNTL); in si_ih_enable_interrupts()
36 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_enable_interrupts()
47 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_disable_interrupts()
48 u32 ih_cntl = RREG32(IH_CNTL); in si_ih_disable_interrupts()
68 interrupt_cntl = RREG32(INTERRUPT_CNTL); in si_ih_irq_init()
116 tmp = RREG32(IH_RB_CNTL); in si_ih_get_wptr()
214 u32 tmp = RREG32(SRBM_STATUS); in si_ih_is_idle()
240 u32 tmp = RREG32(SRBM_STATUS); in si_ih_soft_reset()
246 tmp = RREG32(SRBM_SOFT_RESET); in si_ih_soft_reset()
250 tmp = RREG32(SRBM_SOFT_RESET); in si_ih_soft_reset()
[all …]
Dvce_v3_0.c90 v = RREG32(mmVCE_RB_RPTR); in vce_v3_0_ring_get_rptr()
92 v = RREG32(mmVCE_RB_RPTR2); in vce_v3_0_ring_get_rptr()
94 v = RREG32(mmVCE_RB_RPTR3); in vce_v3_0_ring_get_rptr()
122 v = RREG32(mmVCE_RB_WPTR); in vce_v3_0_ring_get_wptr()
124 v = RREG32(mmVCE_RB_WPTR2); in vce_v3_0_ring_get_wptr()
126 v = RREG32(mmVCE_RB_WPTR3); in vce_v3_0_ring_get_wptr()
182 data = RREG32(mmVCE_CLOCK_GATING_B); in vce_v3_0_set_vce_sw_clock_gating()
187 data = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
192 data = RREG32(mmVCE_UENC_CLOCK_GATING_2); in vce_v3_0_set_vce_sw_clock_gating()
197 data = RREG32(mmVCE_UENC_REG_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
[all …]
Damdgpu_amdkfd_gfx_v7.c277 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) in kgd_set_pasid_vmid_mapping()
385 (*dump)[i++][1] = RREG32(addr); \ in kgd_hqd_dump()
427 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load()
435 data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL); in kgd_hqd_sdma_load()
440 data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL); in kgd_hqd_sdma_load()
510 act = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
515 if (low == RREG32(mmCP_HQD_PQ_BASE) && in kgd_hqd_is_occupied()
516 high == RREG32(mmCP_HQD_PQ_BASE_HI)) in kgd_hqd_is_occupied()
533 sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); in kgd_hqd_sdma_is_occupied()
580 temp = RREG32(mmCP_HQD_IQ_TIMER); in kgd_hqd_destroy()
[all …]
Damdgpu_amdkfd_gfx_v8.c234 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) in kgd_set_pasid_vmid_mapping()
308 value = RREG32(mmRLC_CP_SCHEDULERS); in kgd_hqd_load()
370 (*dump)[i++][1] = RREG32(addr); \ in kgd_hqd_dump()
411 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load()
419 data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL); in kgd_hqd_sdma_load()
424 data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL); in kgd_hqd_sdma_load()
503 act = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
508 if (low == RREG32(mmCP_HQD_PQ_BASE) && in kgd_hqd_is_occupied()
509 high == RREG32(mmCP_HQD_PQ_BASE_HI)) in kgd_hqd_is_occupied()
526 sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); in kgd_hqd_sdma_is_occupied()
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Dsi_smc.c86 original_data = RREG32(SMC_IND_DATA_0); in amdgpu_si_copy_bytes_to_smc()
124 RREG32(CB_CGTT_SCLK_CTRL); in amdgpu_si_reset_smc()
125 RREG32(CB_CGTT_SCLK_CTRL); in amdgpu_si_reset_smc()
126 RREG32(CB_CGTT_SCLK_CTRL); in amdgpu_si_reset_smc()
127 RREG32(CB_CGTT_SCLK_CTRL); in amdgpu_si_reset_smc()
176 tmp = RREG32(SMC_RESP_0); in amdgpu_si_send_msg_to_smc()
182 return (PPSMC_Result)RREG32(SMC_RESP_0); in amdgpu_si_send_msg_to_smc()
254 *value = RREG32(SMC_IND_DATA_0); in amdgpu_si_read_smc_sram_dword()
Dgfx_v7_0.c1625 data = RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_active_bitmap()
1626 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_active_bitmap()
1831 RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v7_0_setup_rb()
1833 RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_setup_rb()
1835 RREG32(mmPA_SC_RASTER_CONFIG); in gfx_v7_0_setup_rb()
1837 RREG32(mmPA_SC_RASTER_CONFIG_1); in gfx_v7_0_setup_rb()
1995 tmp = RREG32(mmSPI_CONFIG_CNTL); in gfx_v7_0_constants_init()
2003 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; in gfx_v7_0_constants_init()
2007 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; in gfx_v7_0_constants_init()
2011 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; in gfx_v7_0_constants_init()
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