Lines Matching refs:RREG32
1625 data = RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_active_bitmap()
1626 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_active_bitmap()
1831 RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v7_0_setup_rb()
1833 RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_setup_rb()
1835 RREG32(mmPA_SC_RASTER_CONFIG); in gfx_v7_0_setup_rb()
1837 RREG32(mmPA_SC_RASTER_CONFIG_1); in gfx_v7_0_setup_rb()
1995 tmp = RREG32(mmSPI_CONFIG_CNTL); in gfx_v7_0_constants_init()
2003 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; in gfx_v7_0_constants_init()
2007 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; in gfx_v7_0_constants_init()
2011 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; in gfx_v7_0_constants_init()
2044 tmp = RREG32(mmSPI_ARB_PRIORITY); in gfx_v7_0_constants_init()
2110 tmp = RREG32(scratch); in gfx_v7_0_ring_test_ring()
2387 tmp = RREG32(scratch); in gfx_v7_0_ring_test_ib()
2667 return RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_get_wptr_gfx()
2675 (void)RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_set_wptr_gfx()
2895 tmp = RREG32(mmCP_HPD_EOP_CONTROL); in gfx_v7_0_compute_pipe_init()
2909 if (RREG32(mmCP_HQD_ACTIVE) & 1) { in gfx_v7_0_mqd_deactivate()
2912 if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) in gfx_v7_0_mqd_deactivate()
2947 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v7_0_mqd_init()
2958 mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL); in gfx_v7_0_mqd_init()
2967 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); in gfx_v7_0_mqd_init()
3002 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v7_0_mqd_init()
3021 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); in gfx_v7_0_mqd_init()
3027 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL); in gfx_v7_0_mqd_init()
3028 mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR); in gfx_v7_0_mqd_init()
3029 mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI); in gfx_v7_0_mqd_init()
3030 mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR); in gfx_v7_0_mqd_init()
3031 mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE); in gfx_v7_0_mqd_init()
3032 mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD); in gfx_v7_0_mqd_init()
3033 mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE); in gfx_v7_0_mqd_init()
3034 mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO); in gfx_v7_0_mqd_init()
3035 mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI); in gfx_v7_0_mqd_init()
3036 mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO); in gfx_v7_0_mqd_init()
3037 mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI); in gfx_v7_0_mqd_init()
3038 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); in gfx_v7_0_mqd_init()
3039 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); in gfx_v7_0_mqd_init()
3040 mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); in gfx_v7_0_mqd_init()
3041 mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); in gfx_v7_0_mqd_init()
3042 mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR); in gfx_v7_0_mqd_init()
3058 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); in gfx_v7_0_mqd_commit()
3119 tmp = RREG32(mmCP_CPF_DEBUG); in gfx_v7_0_cp_compute_resume()
3170 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_enable_gui_idle_interrupt()
3356 tmp = RREG32(mmRLC_LB_CNTL); in gfx_v7_0_enable_lbpw()
3374 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) in gfx_v7_0_wait_for_rlc_serdes()
3388 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) in gfx_v7_0_wait_for_rlc_serdes()
3398 tmp = RREG32(mmRLC_CNTL); in gfx_v7_0_update_rlc()
3407 orig = data = RREG32(mmRLC_CNTL); in gfx_v7_0_halt_rlc()
3416 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) in gfx_v7_0_halt_rlc()
3442 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) in gfx_v7_0_set_safe_mode()
3448 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) in gfx_v7_0_set_safe_mode()
3496 u32 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_rlc_reset()
3534 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; in gfx_v7_0_rlc_resume()
3577 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); in gfx_v7_0_enable_cgcg()
3603 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3604 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3605 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3606 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3623 orig = data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3630 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v7_0_enable_mgcg()
3650 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
3665 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v7_0_enable_mgcg()
3670 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3676 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3682 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
3721 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pu()
3735 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pd()
3748 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_cp_pg()
3761 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gds_pg()
3784 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_cgpg()
3789 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); in gfx_v7_0_enable_gfx_cgpg()
3794 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_cgpg()
3799 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); in gfx_v7_0_enable_gfx_cgpg()
3804 data = RREG32(mmDB_RENDER_CONTROL); in gfx_v7_0_enable_gfx_cgpg()
3826 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); in gfx_v7_0_get_cu_active_bitmap()
3827 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); in gfx_v7_0_get_cu_active_bitmap()
3843 tmp = RREG32(mmRLC_MAX_PG_CU); in gfx_v7_0_init_ao_cu_mask()
3854 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_static_mgpg()
3868 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_dynamic_mgpg()
3901 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_init_gfx_cgpg()
3909 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); in gfx_v7_0_init_gfx_cgpg()
3917 data = RREG32(mmRLC_PG_DELAY_2); in gfx_v7_0_init_gfx_cgpg()
3922 data = RREG32(mmRLC_AUTO_PG_CTRL); in gfx_v7_0_init_gfx_cgpg()
4084 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | in gfx_v7_0_get_gpu_clock_counter()
4085 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); in gfx_v7_0_get_gpu_clock_counter()
4148 return RREG32(mmSQ_IND_DATA); in wave_read_ind()
4163 *(out++) = RREG32(mmSQ_IND_DATA); in wave_read_regs()
4338 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); in gfx_v7_0_gpu_early_init()
4339 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v7_0_gpu_early_init()
4346 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); in gfx_v7_0_gpu_early_init()
4350 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); in gfx_v7_0_gpu_early_init()
4600 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) in gfx_v7_0_is_idle()
4614 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; in gfx_v7_0_wait_for_idle()
4630 tmp = RREG32(mmGRBM_STATUS); in gfx_v7_0_soft_reset()
4646 tmp = RREG32(mmGRBM_STATUS2); in gfx_v7_0_soft_reset()
4651 tmp = RREG32(mmSRBM_STATUS); in gfx_v7_0_soft_reset()
4670 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4674 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4680 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4684 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4688 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4694 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4709 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4714 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4760 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4765 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4783 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
4788 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
4808 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_inst_fault_state()
4813 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_inst_fault_state()
5099 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v7_0_set_gds_init()
5102 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID); in gfx_v7_0_set_gds_init()