96 	blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);  in gmc_v7_0_mc_stop()
114 	tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);  in gmc_v7_0_mc_resume()
203 	running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);  in gmc_v7_0_mc_load_microcode()
226 			if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),  in gmc_v7_0_mc_load_microcode()
232 			if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),  in gmc_v7_0_mc_load_microcode()
245 	u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;  in gmc_v7_0_vram_gtt_location()
280 		tmp = RREG32(mmVGA_HDP_CONTROL);  in gmc_v7_0_mc_program()
285 		tmp = RREG32(mmVGA_RENDER_CONTROL);  in gmc_v7_0_mc_program()
305 	tmp = RREG32(mmHDP_MISC_CNTL);  in gmc_v7_0_mc_program()
309 	tmp = RREG32(mmHDP_HOST_PATH_CNTL);  in gmc_v7_0_mc_program()
332 		tmp = RREG32(mmMC_ARB_RAMCFG);  in gmc_v7_0_mc_init()
338 		tmp = RREG32(mmMC_SHARED_CHMAP);  in gmc_v7_0_mc_init()
372 	adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in gmc_v7_0_mc_init()
373 	adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in gmc_v7_0_mc_init()
385 		adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;  in gmc_v7_0_mc_init()
498 	tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_set_fault_enable_default()
529 	tmp = RREG32(mmVM_PRT_CNTL);  in gmc_v7_0_set_prt()
599 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);  in gmc_v7_0_gart_enable()
607 	tmp = RREG32(mmVM_L2_CNTL);  in gmc_v7_0_gart_enable()
621 	tmp = RREG32(mmVM_L2_CNTL3);  in gmc_v7_0_gart_enable()
633 	tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_gart_enable()
663 	tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_gart_enable()
675 		tmp = RREG32(mmCHUB_CONTROL);  in gmc_v7_0_gart_enable()
720 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);  in gmc_v7_0_gart_disable()
726 	tmp = RREG32(mmVM_L2_CNTL);  in gmc_v7_0_gart_disable()
806 		orig = data = RREG32(mc_cg_registers[i]);  in gmc_v7_0_enable_mc_ls()
823 		orig = data = RREG32(mc_cg_registers[i]);  in gmc_v7_0_enable_mc_mgcg()
861 	orig = data = RREG32(mmHDP_HOST_PATH_CNTL);  in gmc_v7_0_enable_hdp_mgcg()
877 	orig = data = RREG32(mmHDP_MEM_POWER_LS);  in gmc_v7_0_enable_hdp_ls()
942 	u32 d1vga_control = RREG32(mmD1VGA_CONTROL);  in gmc_v7_0_get_vbios_fb_size()
948 		u32 viewport = RREG32(mmVIEWPORT_SIZE);  in gmc_v7_0_get_vbios_fb_size()
969 		u32 tmp = RREG32(mmMC_SEQ_MISC0);  in gmc_v7_0_sw_init()
1033 		u64 tmp = RREG32(mmMC_VM_FB_OFFSET);  in gmc_v7_0_sw_init()
1126 	u32 tmp = RREG32(mmSRBM_STATUS);  in gmc_v7_0_is_idle()
1143 		tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |  in gmc_v7_0_wait_for_idle()
1160 	u32 tmp = RREG32(mmSRBM_STATUS);  in gmc_v7_0_soft_reset()
1180 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1184 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1190 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1218 		tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1222 		tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1228 		tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1232 		tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1249 	addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);  in gmc_v7_0_process_interrupt()
1250 	status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);  in gmc_v7_0_process_interrupt()
1251 	mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);  in gmc_v7_0_process_interrupt()