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Searched refs:PIPE_A (Results 1 – 25 of 28) sorted by relevance

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/Linux-v5.4/drivers/gpu/drm/i915/gvt/
Dhandlers.c1959 MMIO_D(PIPEDSL(PIPE_A), D_ALL); in init_generic_mmio_info()
1964 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
1969 MMIO_D(PIPESTAT(PIPE_A), D_ALL); in init_generic_mmio_info()
1974 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); in init_generic_mmio_info()
1979 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); in init_generic_mmio_info()
1984 MMIO_D(CURCNTR(PIPE_A), D_ALL); in init_generic_mmio_info()
1988 MMIO_D(CURPOS(PIPE_A), D_ALL); in init_generic_mmio_info()
1992 MMIO_D(CURBASE(PIPE_A), D_ALL); in init_generic_mmio_info()
1996 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL); in init_generic_mmio_info()
2009 MMIO_D(DSPCNTR(PIPE_A), D_ALL); in init_generic_mmio_info()
[all …]
Ddisplay.c46 pipe = PIPE_A; in get_edp_pipe()
74 if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
305 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
395 [PIPE_A] = PIPE_A_VBLANK, in emulate_vblank_on_pipe()
401 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()
Dreg.h72 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
82 (((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
Dcmd_parser.c1216 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE}, in gen8_decode_mi_display_flip()
1218 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE}, in gen8_decode_mi_display_flip()
1271 info->pipe = PIPE_A; in skl_decode_mi_display_flip()
1284 info->pipe = PIPE_A; in skl_decode_mi_display_flip()
Dinterrupt.c449 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A));
/Linux-v5.4/drivers/gpu/drm/i915/display/
Dintel_ddi.c1085 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | in hsw_fdi_link_train()
1093 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1094 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1099 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1129 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); in hsw_fdi_link_train()
1133 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1134 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1140 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
1142 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); in hsw_fdi_link_train()
1143 POSTING_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
[all …]
Dintel_crt.c235 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_disable_crt()
255 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_post_disable_crt()
266 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_pre_pll_enable_crt()
301 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_enable_crt()
1069 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()
Dintel_pipe_crc.c179 case PIPE_A: in vlv_pipe_crc_ctl_reg()
243 case PIPE_A: in vlv_undo_pipe_scramble_reset()
316 pipe_config->base.active && crtc->pipe == PIPE_A && in intel_crtc_crc_setup_workarounds()
Dintel_fifo_underrun.c133 u32 bit = (pipe == PIPE_A) ? in ironlake_set_fifo_underrun_reporting()
199 u32 bit = (pch_transcoder == PIPE_A) ? in ibx_set_fifo_underrun_reporting()
Dintel_display_power.c1027 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1028 i830_enable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_enable()
1037 i830_disable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_disable()
1043 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled()
1184 if (pipe != PIPE_A) in vlv_display_power_well_init()
1404 pipe = PIPE_A; in chv_dpio_cmn_power_well_enable()
1464 assert_pll_disabled(dev_priv, PIPE_A); in chv_dpio_cmn_power_well_disable()
1488 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; in assert_chv_phy_powergate()
1611 enum pipe pipe = PIPE_A; in chv_pipe_power_well_enabled()
1641 enum pipe pipe = PIPE_A; in chv_set_pipe_power_well()
[all …]
Dintel_display.h82 PIPE_A = 0, enumerator
100 TRANSCODER_A = PIPE_A,
Dintel_display.c1452 if (pipe != PIPE_A) { in chv_enable_pll()
1555 if (pipe != PIPE_A) in vlv_disable_pll()
1572 if (pipe != PIPE_A) in chv_disable_pll()
1684 assert_fdi_rx_enabled(dev_priv, PIPE_A); in lpt_enable_pch_transcoder()
1687 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder()
1689 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); in lpt_enable_pch_transcoder()
1749 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); in lpt_disable_pch_transcoder()
1751 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); in lpt_disable_pch_transcoder()
1759 return PIPE_A; in intel_crtc_pch_transcoder()
2506 crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); in intel_plane_fb_max_stride()
[all …]
Dintel_dp.c799 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
853 pipe = PIPE_A; in vlv_power_sequencer_pipe()
928 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
3092 *pipe = PIPE_A; in cpt_dp_port_selected()
3494 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
4102 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
4103 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
4107 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | in intel_dp_link_down()
4116 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_dp_link_down()
4117 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_dp_link_down()
[all …]
Dintel_hdmi.c2016 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
2017 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
2020 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_hdmi()
2034 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_hdmi()
2035 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
2036 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
Dintel_sdvo.c1752 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_sdvo()
1753 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_sdvo()
1756 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_sdvo()
1762 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_sdvo()
1763 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_sdvo()
1764 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_sdvo()
Dicl_dsi.c739 case PIPE_A: in gen11_dsi_configure_transcoder()
1320 *pipe = PIPE_A; in gen11_dsi_get_hw_state()
1587 encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); in icl_dsi_init()
Dvlv_dsi.c1016 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1873 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); in vlv_dsi_init()
1875 intel_encoder->crtc_mask = BIT(PIPE_A); in vlv_dsi_init()
Dintel_display_types.h1329 case PIPE_A: in vlv_pipe_to_channel()
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_pci.c98 [PIPE_A] = CURSOR_A_OFFSET, \
103 [PIPE_A] = CURSOR_A_OFFSET, \
109 [PIPE_A] = CURSOR_A_OFFSET, \
116 [PIPE_A] = CURSOR_A_OFFSET, \
Di915_trace.h44 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
71 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
168 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
Dintel_pm.c503 case PIPE_A: in vlv_get_fifo_size()
961 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in g4x_write_wm_values()
967 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in g4x_write_wm_values()
968 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in g4x_write_wm_values()
1011 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in vlv_write_wm_values()
1013 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | in vlv_write_wm_values()
1014 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in vlv_write_wm_values()
1015 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in vlv_write_wm_values()
1037 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
1038 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
[all …]
Dintel_device_info.c869 runtime->num_scalers[PIPE_A] = 2; in intel_device_info_runtime_init()
892 runtime->num_sprites[PIPE_A] = 2; in intel_device_info_runtime_init()
936 enabled_mask &= ~BIT(PIPE_A); in intel_device_info_runtime_init()
Di915_irq.c701 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()
1744 case PIPE_A: in i9xx_pipestat_irq_ack()
2179 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); in ibx_irq_handler()
3192 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in vlv_display_irq_postinstall()
3931 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
4105 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
4222 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_irq_postinstall()
4223 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/Linux-v5.4/drivers/video/fbdev/intelfb/
Dintelfbhw.c482 if (unlikely(pipe == PIPE_A)) in intelfbhw_active_pipe()
483 return PIPE_A; in intelfbhw_active_pipe()
488 if (likely(pipe == PIPE_A)) in intelfbhw_active_pipe()
489 return PIPE_A; in intelfbhw_active_pipe()
494 pipe = PIPE_A; in intelfbhw_active_pipe()
503 u32 palette_reg = (dinfo->pipe == PIPE_A) ? in intelfbhw_setcolreg()
Dintelfbhw.h182 #define PIPE_A 0 macro

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