1085 	I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |  in hsw_fdi_link_train()
1093 	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);  in hsw_fdi_link_train()
1094 	POSTING_READ(FDI_RX_CTL(PIPE_A));  in hsw_fdi_link_train()
1099 	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);  in hsw_fdi_link_train()
1129 		I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));  in hsw_fdi_link_train()
1133 		I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);  in hsw_fdi_link_train()
1134 		POSTING_READ(FDI_RX_CTL(PIPE_A));  in hsw_fdi_link_train()
1140 		temp = I915_READ(FDI_RX_MISC(PIPE_A));  in hsw_fdi_link_train()
1142 		I915_WRITE(FDI_RX_MISC(PIPE_A), temp);  in hsw_fdi_link_train()
1143 		POSTING_READ(FDI_RX_MISC(PIPE_A));  in hsw_fdi_link_train()
1164 		I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);  in hsw_fdi_link_train()
1165 		POSTING_READ(FDI_RX_CTL(PIPE_A));  in hsw_fdi_link_train()
1182 		temp = I915_READ(FDI_RX_MISC(PIPE_A));  in hsw_fdi_link_train()
1185 		I915_WRITE(FDI_RX_MISC(PIPE_A), temp);  in hsw_fdi_link_train()
1186 		POSTING_READ(FDI_RX_MISC(PIPE_A));  in hsw_fdi_link_train()
1805 		case PIPE_A:  in intel_ddi_enable_transcoder_func()
2001 			*pipe_mask = BIT(PIPE_A);  in intel_ddi_get_encoder_pipes()
3444 	val = I915_READ(FDI_RX_CTL(PIPE_A));  in intel_ddi_fdi_post_disable()
3446 	I915_WRITE(FDI_RX_CTL(PIPE_A), val);  in intel_ddi_fdi_post_disable()
3451 	val = I915_READ(FDI_RX_MISC(PIPE_A));  in intel_ddi_fdi_post_disable()
3454 	I915_WRITE(FDI_RX_MISC(PIPE_A), val);  in intel_ddi_fdi_post_disable()
3456 	val = I915_READ(FDI_RX_CTL(PIPE_A));  in intel_ddi_fdi_post_disable()
3458 	I915_WRITE(FDI_RX_CTL(PIPE_A), val);  in intel_ddi_fdi_post_disable()
3460 	val = I915_READ(FDI_RX_CTL(PIPE_A));  in intel_ddi_fdi_post_disable()
3462 	I915_WRITE(FDI_RX_CTL(PIPE_A), val);  in intel_ddi_fdi_post_disable()
3989 	if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&  in intel_ddi_compute_config()