1452 	if (pipe != PIPE_A) {  in chv_enable_pll()
1555 	if (pipe != PIPE_A)  in vlv_disable_pll()
1572 	if (pipe != PIPE_A)  in chv_disable_pll()
1684 	assert_fdi_rx_enabled(dev_priv, PIPE_A);  in lpt_enable_pch_transcoder()
1687 	val = I915_READ(TRANS_CHICKEN2(PIPE_A));  in lpt_enable_pch_transcoder()
1689 	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);  in lpt_enable_pch_transcoder()
1749 	val = I915_READ(TRANS_CHICKEN2(PIPE_A));  in lpt_disable_pch_transcoder()
1751 	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);  in lpt_disable_pch_transcoder()
1759 		return PIPE_A;  in intel_crtc_pch_transcoder()
2506 	crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);  in intel_plane_fb_max_stride()
5157 	case PIPE_A:  in ivybridge_update_fdi_bc_bifurcation()
5303 	assert_pch_transcoder_disabled(dev_priv, PIPE_A);  in lpt_pch_enable()
5308 	ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);  in lpt_pch_enable()
6403 	return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;  in hsw_crtc_supports_ips()
7212 	case PIPE_A:  in ironlake_check_fdi_lanes()
7368 		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));  in intel_crtc_supports_double_wide()
7709 	if (crtc->pipe != PIPE_A)  in vlv_compute_dpll()
7726 	if (crtc->pipe != PIPE_A)  in chv_compute_dpll()
7810 		if (pipe == PIPE_A)  in vlv_prepare_pll()
7818 		if (pipe == PIPE_A)  in vlv_prepare_pll()
8830 		if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)  in i9xx_get_pipe_config()
10259 			trans_pipe = PIPE_A;  in hsw_get_transcoder_state()
10392 		tmp = I915_READ(FDI_RX_CTL(PIPE_A));  in haswell_get_ddi_port_state()
10731 		I915_WRITE_FW(CURCNTR(PIPE_A), 0);  in i845_update_cursor()
10732 		I915_WRITE_FW(CURBASE(PIPE_A), base);  in i845_update_cursor()
10734 		I915_WRITE_FW(CURPOS(PIPE_A), pos);  in i845_update_cursor()
10735 		I915_WRITE_FW(CURCNTR(PIPE_A), cntl);  in i845_update_cursor()
10741 		I915_WRITE_FW(CURPOS(PIPE_A), pos);  in i845_update_cursor()
10761 	power_domain = POWER_DOMAIN_PIPE(PIPE_A);  in i845_cursor_get_hw_state()
10766 	ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;  in i845_cursor_get_hw_state()
10768 	*pipe = PIPE_A;  in i845_cursor_get_hw_state()
16365 	WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);  in i830_disable_pipe()
16431 		(HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);  in has_pch_trancoder()
16637 		enum pipe pipe = PIPE_A;  in readout_plane_state()
16884 	    (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))  in ibx_sanitize_pch_hdmi_port()
16891 	val |= SDVO_PIPE_SEL(PIPE_A);  in ibx_sanitize_pch_hdmi_port()
16902 	    (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))  in ibx_sanitize_pch_dp_port()
16909 	val |= DP_PIPE_SEL(PIPE_A);  in ibx_sanitize_pch_dp_port()