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Searched refs:GC (Results 1 – 25 of 25) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
[all …]
Dgfx_v9_4.c42 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1 },
43 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1 },
45 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1 },
46 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1 },
47 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1 },
49 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1 },
50 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1 },
52 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1 },
53 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1 },
54 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1 },
[all …]
Dgfxhub_v1_0.c35 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; in gfxhub_v1_0_get_mc_fb_offset()
43 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v1_0_setup_vm_pt_regs()
47 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v1_0_setup_vm_pt_regs()
58 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
60 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
63 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
65 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
74 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0); in gfxhub_v1_0_init_system_aperture_regs()
75 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v1_0_init_system_aperture_regs()
76 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v1_0_init_system_aperture_regs()
[all …]
Dgfxhub_v2_1.c107 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); in gfxhub_v2_1_get_fb_location()
117 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; in gfxhub_v2_1_get_mc_fb_offset()
125 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v2_1_setup_vm_pt_regs()
129 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v2_1_setup_vm_pt_regs()
140 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v2_1_init_gart_aperture_regs()
142 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v2_1_init_gart_aperture_regs()
145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v2_1_init_gart_aperture_regs()
147 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v2_1_init_gart_aperture_regs()
156 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_1_init_system_aperture_regs()
157 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); in gfxhub_v2_1_init_system_aperture_regs()
[all …]
Dgfx_v9_0.c509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000),
511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x00ffff87),
[all …]
Dgfxhub_v2_0.c107 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); in gfxhub_v2_0_get_fb_location()
117 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; in gfxhub_v2_0_get_mc_fb_offset()
125 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v2_0_setup_vm_pt_regs()
129 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v2_0_setup_vm_pt_regs()
140 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs()
142 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs()
145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs()
147 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs()
157 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_0_init_system_aperture_regs()
158 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); in gfxhub_v2_0_init_system_aperture_regs()
[all …]
Dmes_v10_1.c420 data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); in mes_v10_1_enable()
422 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
425 WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START, in mes_v10_1_enable()
429 data = RREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL); in mes_v10_1_enable()
432 WREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL, data); in mes_v10_1_enable()
436 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
438 data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); in mes_v10_1_enable()
444 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
469 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_CNTL, 0); in mes_v10_1_load_microcode()
476 WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START, in mes_v10_1_load_microcode()
[all …]
Damdgpu_amdkfd_gfx_v10_3.c99 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); in program_sh_mem_settings_v10_3()
100 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in program_sh_mem_settings_v10_3()
133 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), in init_interrupts_v10_3()
216 value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); in hqd_load_v10_3()
219 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); in hqd_load_v10_3()
224 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in hqd_load_v10_3()
227 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in hqd_load_v10_3()
234 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); in hqd_load_v10_3()
263 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), in hqd_load_v10_3()
265 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), in hqd_load_v10_3()
[all …]
Damdgpu_amdkfd_gfx_v10.c100 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); in kgd_program_sh_mem_settings()
101 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in kgd_program_sh_mem_settings()
165 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), in kgd_init_interrupts()
203 uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) -
239 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_hqd_load()
242 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_hqd_load()
249 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); in kgd_hqd_load()
278 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), in kgd_hqd_load()
280 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), in kgd_hqd_load()
282 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), in kgd_hqd_load()
[all …]
Damdgpu_amdkfd_gfx_v9.c104 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); in kgd_gfx_v9_program_sh_mem_settings()
105 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings()
183 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), in kgd_gfx_v9_init_interrupts()
250 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_gfx_v9_hqd_load()
253 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_gfx_v9_hqd_load()
260 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); in kgd_gfx_v9_hqd_load()
289 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), in kgd_gfx_v9_hqd_load()
291 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), in kgd_gfx_v9_hqd_load()
293 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), in kgd_gfx_v9_hqd_load()
295 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), in kgd_gfx_v9_hqd_load()
[all …]
Dsdma_v5_0.c66 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
67 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
[all …]
Dsoc15.c173 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); in soc15_didt_rreg()
174 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); in soc15_didt_rreg()
187 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); in soc15_didt_wreg()
188 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); in soc15_didt_wreg()
202 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); in soc15_gc_cac_rreg()
203 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); in soc15_gc_cac_rreg()
213 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); in soc15_gc_cac_wreg()
214 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); in soc15_gc_cac_wreg()
224 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); in soc15_se_cac_rreg()
225 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); in soc15_se_cac_rreg()
[all …]
Dnv.c113 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); in nv_didt_rreg()
114 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); in nv_didt_rreg()
127 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); in nv_didt_wreg()
128 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); in nv_didt_wreg()
156 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); in nv_grbm_select()
197 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
198 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
199 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
200 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
201 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
[all …]
Dgfxhub_v1_1.c34 u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL); in gfxhub_v1_1_get_xgmi_info()
64 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE), in gfxhub_v1_1_get_xgmi_info()
Damdgpu_discovery.c220 info = &bhdr->table_list[GC]; in amdgpu_discovery_init()
387 le16_to_cpu(bhdr->table_list[GC].offset)); in amdgpu_discovery_get_gfx_info()
Dmmhub_v2_0.c299 WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp); in mmhub_v2_0_init_cache_regs()
/Linux-v5.10/fs/jffs2/
DTODO4 space it could take. Let GC flush the outstanding writes because the
9 - fine-tune the allocation / GC thresholds
27 closer to 100% or 0% clean, hence speeding up later GC progress dramatically.
DREADME.Locking95 GC thread locks it, sends the signal, then unlocks it - while the GC
/Linux-v5.10/Documentation/ABI/testing/
Dsysfs-fs-f2fs127 section, it can let GC move partial segment{s} of one section
128 in one GC cycle, so that dispersing heavy overhead GC to
241 Description: Do background GC agressively when set. When gc_urgent = 1,
242 background thread starts to do GC by given gc_urgent_sleep_time
245 and GC a little bit aggressively. It is set to 0 by default.
250 Description: Controls sleep time of GC urgent mode. Set to 500ms by default.
260 Description: This indicates how many GC can be failed for the pinned
/Linux-v5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega10_powertune.c923 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_cac_driving_se_didt_config()
938 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_cac_driving_se_didt_config()
974 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_psm_gc_didt_config()
983 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_psm_gc_didt_config()
1035 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_se_edc_config()
1046 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_se_edc_config()
1085 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_psm_gc_edc_config()
1094 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_psm_gc_edc_config()
1144 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_se_edc_force_stall_config()
/Linux-v5.10/drivers/gpu/drm/amd/include/
Ddiscovery.h34 GC, enumerator
/Linux-v5.10/Documentation/admin-guide/media/
Dgspca-cardlist.rst166 sunplus 04f1:1001 JVC GC A50
/Linux-v5.10/Documentation/filesystems/
Df2fs.rst270 effectiveness and efficiency on background GC.
/Linux-v5.10/Documentation/networking/
Dip-sysctl.rst225 passes. More entries, less time-to-live, less GC interval.
/Linux-v5.10/
DCREDITS2909 D: Author of mark-and-sweep GC integrated by Alan Cox