Lines Matching refs:GC
509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000),
511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x00ffff87),
519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x00ffff8f),
520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800),
528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000)
533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800),
550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080),
556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042),
560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400),
561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000),
562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000),
563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),
565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000)
570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800),
593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000)
598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000),
610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080),
613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080),
614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080),
615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041),
616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041),
617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080),
620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080),
621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080),
622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080),
623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080),
624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010),
626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042),
636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042),
637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc),
648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff),
649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080),
676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041),
679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041),
680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800),
687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000)
692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000),
694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e),
695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca),
696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098),
697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3),
698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1),
699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),
701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00),
702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000)
706 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)},
707 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)},
996 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_scratch_init()
1762 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap); in gfx_v9_0_init_always_on_cu_mask()
1772 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap); in gfx_v9_0_init_always_on_cu_mask()
1785 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); in gfx_v9_0_init_lbpw()
1786 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); in gfx_v9_0_init_lbpw()
1787 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); in gfx_v9_0_init_lbpw()
1788 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); in gfx_v9_0_init_lbpw()
1791 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); in gfx_v9_0_init_lbpw()
1794 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); in gfx_v9_0_init_lbpw()
1799 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); in gfx_v9_0_init_lbpw()
1805 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); in gfx_v9_0_init_lbpw()
1808 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); in gfx_v9_0_init_lbpw()
1811 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); in gfx_v9_0_init_lbpw()
1823 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); in gfx_v9_0_init_lbpw()
1834 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); in gfx_v9_4_init_lbpw()
1835 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8); in gfx_v9_4_init_lbpw()
1836 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); in gfx_v9_4_init_lbpw()
1837 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16)); in gfx_v9_4_init_lbpw()
1840 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); in gfx_v9_4_init_lbpw()
1843 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800); in gfx_v9_4_init_lbpw()
1848 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); in gfx_v9_4_init_lbpw()
1854 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); in gfx_v9_4_init_lbpw()
1857 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); in gfx_v9_4_init_lbpw()
1860 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); in gfx_v9_4_init_lbpw()
1872 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); in gfx_v9_4_init_lbpw()
1880 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_lbpw()
1998 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, in wave_read_ind()
2003 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); in wave_read_ind()
2010 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, in wave_read_regs()
2018 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); in wave_read_regs()
2122 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); in gfx_v9_0_gpu_early_init()
2148 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); in gfx_v9_0_gpu_early_init()
2158 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); in gfx_v9_0_gpu_early_init()
2430 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); in gfx_v9_0_select_se_sh()
2437 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); in gfx_v9_0_get_rb_active_bitmap()
2438 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); in gfx_v9_0_get_rb_active_bitmap()
2496 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); in gfx_v9_0_init_compute_vmid()
2497 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in gfx_v9_0_init_compute_vmid()
2505 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); in gfx_v9_0_init_compute_vmid()
2506 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); in gfx_v9_0_init_compute_vmid()
2507 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); in gfx_v9_0_init_compute_vmid()
2508 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); in gfx_v9_0_init_compute_vmid()
2523 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); in gfx_v9_0_init_gds_vmid()
2524 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); in gfx_v9_0_init_gds_vmid()
2525 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); in gfx_v9_0_init_gds_vmid()
2526 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); in gfx_v9_0_init_gds_vmid()
2536 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG); in gfx_v9_0_init_sq_config()
2539 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp); in gfx_v9_0_init_sq_config()
2551 WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); in gfx_v9_0_constants_init()
2557 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); in gfx_v9_0_constants_init()
2570 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); in gfx_v9_0_constants_init()
2571 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); in gfx_v9_0_constants_init()
2577 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); in gfx_v9_0_constants_init()
2582 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); in gfx_v9_0_constants_init()
2604 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) in gfx_v9_0_wait_for_rlc_serdes()
2626 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) in gfx_v9_0_wait_for_rlc_serdes()
2635 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); in gfx_v9_0_enable_gui_idle_interrupt()
2642 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); in gfx_v9_0_enable_gui_idle_interrupt()
2649 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), in gfx_v9_0_init_csb()
2651 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), in gfx_v9_0_init_csb()
2653 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), in gfx_v9_0_init_csb()
2724 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); in gfx_v9_1_init_rlc_save_restore_list()
2726 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); in gfx_v9_1_init_rlc_save_restore_list()
2729 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), in gfx_v9_1_init_rlc_save_restore_list()
2732 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), in gfx_v9_1_init_rlc_save_restore_list()
2736 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), in gfx_v9_1_init_rlc_save_restore_list()
2741 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), in gfx_v9_1_init_rlc_save_restore_list()
2747 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); in gfx_v9_1_init_rlc_save_restore_list()
2751 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); in gfx_v9_1_init_rlc_save_restore_list()
2752 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); in gfx_v9_1_init_rlc_save_restore_list()
2756 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j); in gfx_v9_1_init_rlc_save_restore_list()
2769 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), in gfx_v9_1_init_rlc_save_restore_list()
2771 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); in gfx_v9_1_init_rlc_save_restore_list()
2774 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), in gfx_v9_1_init_rlc_save_restore_list()
2777 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), in gfx_v9_1_init_rlc_save_restore_list()
2783 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) in gfx_v9_1_init_rlc_save_restore_list()
2787 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) in gfx_v9_1_init_rlc_save_restore_list()
2799 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); in gfx_v9_0_enable_save_restore_machine()
2836 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); in gfx_v9_0_init_gfx_power_gating()
2839 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); in gfx_v9_0_init_gfx_power_gating()
2847 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); in gfx_v9_0_init_gfx_power_gating()
2849 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); in gfx_v9_0_init_gfx_power_gating()
2852 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); in gfx_v9_0_init_gfx_power_gating()
2854 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); in gfx_v9_0_init_gfx_power_gating()
2857 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); in gfx_v9_0_init_gfx_power_gating()
2859 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); in gfx_v9_0_init_gfx_power_gating()
2864 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); in gfx_v9_0_init_gfx_power_gating()
2876 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_sck_slow_down_on_power_up()
2881 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_sck_slow_down_on_power_up()
2890 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_sck_slow_down_on_power_down()
2895 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_sck_slow_down_on_power_down()
2904 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_cp_power_gating()
2909 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_cp_power_gating()
2917 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_gfx_cg_power_gating()
2922 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_cg_power_gating()
2930 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_gfx_pipeline_powergating()
2935 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_pipeline_powergating()
2939 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); in gfx_v9_0_enable_gfx_pipeline_powergating()
2947 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_gfx_static_mg_power_gating()
2952 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_static_mg_power_gating()
2960 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_gfx_dynamic_mg_power_gating()
2965 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_dynamic_mg_power_gating()
2997 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v9_0_rlc_stop()
3004 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v9_0_rlc_reset()
3006 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v9_0_rlc_reset()
3016 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v9_0_rlc_start()
3027 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); in gfx_v9_0_rlc_start()
3033 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); in gfx_v9_0_rlc_start()
3037 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); in gfx_v9_0_rlc_start()
3058 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, in gfx_v9_0_rlc_load_microcode()
3061 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); in gfx_v9_0_rlc_load_microcode()
3062 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v9_0_rlc_load_microcode()
3079 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); in gfx_v9_0_rlc_resume()
3114 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); in gfx_v9_0_cp_gfx_enable()
3119 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v9_0_cp_gfx_enable()
3152 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); in gfx_v9_0_cp_gfx_load_microcode()
3154 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); in gfx_v9_0_cp_gfx_load_microcode()
3155 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
3162 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); in gfx_v9_0_cp_gfx_load_microcode()
3164 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); in gfx_v9_0_cp_gfx_load_microcode()
3165 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
3172 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); in gfx_v9_0_cp_gfx_load_microcode()
3174 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); in gfx_v9_0_cp_gfx_load_microcode()
3175 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
3188 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v9_0_cp_gfx_start()
3189 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); in gfx_v9_0_cp_gfx_start()
3233 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); in gfx_v9_0_cp_gfx_start()
3250 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); in gfx_v9_0_cp_gfx_resume()
3253 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); in gfx_v9_0_cp_gfx_resume()
3263 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); in gfx_v9_0_cp_gfx_resume()
3267 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v9_0_cp_gfx_resume()
3268 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v9_0_cp_gfx_resume()
3272 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v9_0_cp_gfx_resume()
3273 …WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_… in gfx_v9_0_cp_gfx_resume()
3276 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); in gfx_v9_0_cp_gfx_resume()
3277 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); in gfx_v9_0_cp_gfx_resume()
3280 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); in gfx_v9_0_cp_gfx_resume()
3283 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); in gfx_v9_0_cp_gfx_resume()
3284 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v9_0_cp_gfx_resume()
3286 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); in gfx_v9_0_cp_gfx_resume()
3295 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); in gfx_v9_0_cp_gfx_resume()
3299 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); in gfx_v9_0_cp_gfx_resume()
3301 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, in gfx_v9_0_cp_gfx_resume()
3315 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); in gfx_v9_0_cp_compute_enable()
3317 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, in gfx_v9_0_cp_compute_enable()
3345 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); in gfx_v9_0_cp_compute_load_microcode()
3347 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, in gfx_v9_0_cp_compute_load_microcode()
3349 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, in gfx_v9_0_cp_compute_load_microcode()
3353 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, in gfx_v9_0_cp_compute_load_microcode()
3356 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, in gfx_v9_0_cp_compute_load_microcode()
3359 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, in gfx_v9_0_cp_compute_load_microcode()
3373 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); in gfx_v9_0_kiq_setting()
3376 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); in gfx_v9_0_kiq_setting()
3378 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); in gfx_v9_0_kiq_setting()
3425 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); in gfx_v9_0_mqd_init()
3432 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v9_0_mqd_init()
3462 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); in gfx_v9_0_mqd_init()
3472 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); in gfx_v9_0_mqd_init()
3500 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v9_0_mqd_init()
3516 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); in gfx_v9_0_mqd_init()
3521 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); in gfx_v9_0_mqd_init()
3526 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); in gfx_v9_0_mqd_init()
3550 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_0_kiq_init_register()
3552 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR, in gfx_v9_0_kiq_init_register()
3554 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, in gfx_v9_0_kiq_init_register()
3558 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL, in gfx_v9_0_kiq_init_register()
3562 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v9_0_kiq_init_register()
3566 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { in gfx_v9_0_kiq_init_register()
3567 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v9_0_kiq_init_register()
3569 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) in gfx_v9_0_kiq_init_register()
3573 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, in gfx_v9_0_kiq_init_register()
3575 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, in gfx_v9_0_kiq_init_register()
3577 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, in gfx_v9_0_kiq_init_register()
3579 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, in gfx_v9_0_kiq_init_register()
3584 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR, in gfx_v9_0_kiq_init_register()
3586 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI, in gfx_v9_0_kiq_init_register()
3590 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL, in gfx_v9_0_kiq_init_register()
3594 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE, in gfx_v9_0_kiq_init_register()
3596 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI, in gfx_v9_0_kiq_init_register()
3600 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL, in gfx_v9_0_kiq_init_register()
3604 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, in gfx_v9_0_kiq_init_register()
3606 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, in gfx_v9_0_kiq_init_register()
3610 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, in gfx_v9_0_kiq_init_register()
3612 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, in gfx_v9_0_kiq_init_register()
3617 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, in gfx_v9_0_kiq_init_register()
3619 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, in gfx_v9_0_kiq_init_register()
3623 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v9_0_kiq_init_register()
3627 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, in gfx_v9_0_kiq_init_register()
3629 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, in gfx_v9_0_kiq_init_register()
3633 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); in gfx_v9_0_kiq_init_register()
3635 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, in gfx_v9_0_kiq_init_register()
3639 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, in gfx_v9_0_kiq_init_register()
3643 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v9_0_kiq_init_register()
3654 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { in gfx_v9_0_kiq_fini_register()
3656 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v9_0_kiq_fini_register()
3659 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) in gfx_v9_0_kiq_fini_register()
3668 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0); in gfx_v9_0_kiq_fini_register()
3671 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, in gfx_v9_0_kiq_fini_register()
3675 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0); in gfx_v9_0_kiq_fini_register()
3676 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0); in gfx_v9_0_kiq_fini_register()
3677 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); in gfx_v9_0_kiq_fini_register()
3678 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); in gfx_v9_0_kiq_fini_register()
3679 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); in gfx_v9_0_kiq_fini_register()
3680 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0); in gfx_v9_0_kiq_fini_register()
3681 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); in gfx_v9_0_kiq_fini_register()
3682 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); in gfx_v9_0_kiq_fini_register()
3872 tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG); in gfx_v9_0_init_tcp_config()
3879 WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp); in gfx_v9_0_init_tcp_config()
3932 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_0_hw_fini()
3969 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), in gfx_v9_0_is_idle()
3996 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); in gfx_v9_0_soft_reset()
4015 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); in gfx_v9_0_soft_reset()
4033 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v9_0_soft_reset()
4036 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in gfx_v9_0_soft_reset()
4037 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v9_0_soft_reset()
4042 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in gfx_v9_0_soft_reset()
4043 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v9_0_soft_reset()
4135 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); in gfx_v9_0_get_gpu_clock_counter()
4136 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | in gfx_v9_0_get_gpu_clock_counter()
4137 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); in gfx_v9_0_get_gpu_clock_counter()
4154 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, in gfx_v9_0_ring_emit_gds_switch()
4159 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, in gfx_v9_0_ring_emit_gds_switch()
4164 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, in gfx_v9_0_ring_emit_gds_switch()
4169 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, in gfx_v9_0_ring_emit_gds_switch()
4306 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
4307 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
4308 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 },
4309 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
4310 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f },
4311 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */
4312 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
4313 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
4314 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
4315 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
4316 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
4317 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
4318 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
4319 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
4323 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
4324 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
4325 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 },
4326 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
4327 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0xbf },
4328 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */
4329 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
4330 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
4331 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
4332 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
4333 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
4334 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
4335 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
4336 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
4340 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
4341 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
4342 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
4343 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
4344 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
4345 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
4346 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff },
4347 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff },
4348 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff },
4349 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff },
4350 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x000000ff },
4351 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x000000ff },
4352 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x000000ff },
4353 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x000000ff },
4357 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
4358 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
4359 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
4360 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
4361 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
4362 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
4363 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 },
4364 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 },
4365 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 },
4366 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 },
4367 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x0000ff00 },
4368 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x0000ff00 },
4369 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x0000ff00 },
4370 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x0000ff00 },
4374 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1},
4375 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1},
4376 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1},
4377 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1},
4378 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1},
4379 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1},
4380 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1},
4381 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1},
4382 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1},
4383 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1},
4384 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1},
4385 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1},
4386 { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1},
4387 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6},
4388 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16},
4389 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16},
4390 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16},
4391 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16},
4392 { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16},
4393 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16},
4394 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16},
4395 { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16},
4396 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6},
4397 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16},
4398 { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16},
4399 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1},
4400 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1},
4401 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32},
4402 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32},
4403 { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72},
4404 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
4405 { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
4406 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
4425 WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000); in gfx_v9_0_do_edc_gds_workarounds()
4426 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); in gfx_v9_0_do_edc_gds_workarounds()
4451 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000); in gfx_v9_0_do_edc_gds_workarounds()
4534 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) in gfx_v9_0_do_edc_gpr_workarounds()
4562 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) in gfx_v9_0_do_edc_gpr_workarounds()
4590 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) in gfx_v9_0_do_edc_gpr_workarounds()
4704 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v9_0_is_rlc_enabled()
4718 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); in gfx_v9_0_set_safe_mode()
4722 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) in gfx_v9_0_set_safe_mode()
4733 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); in gfx_v9_0_unset_safe_mode()
4783 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v9_0_update_medium_grain_clock_gating()
4796 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v9_0_update_medium_grain_clock_gating()
4802 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4805 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
4809 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4812 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
4817 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v9_0_update_medium_grain_clock_gating()
4828 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v9_0_update_medium_grain_clock_gating()
4831 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4834 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
4838 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4841 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
4861 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v9_0_update_3d_clock_gating()
4866 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v9_0_update_3d_clock_gating()
4869 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); in gfx_v9_0_update_3d_clock_gating()
4877 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v9_0_update_3d_clock_gating()
4880 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v9_0_update_3d_clock_gating()
4884 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v9_0_update_3d_clock_gating()
4887 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); in gfx_v9_0_update_3d_clock_gating()
4893 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v9_0_update_3d_clock_gating()
4907 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v9_0_update_coarse_grain_clock_gating()
4916 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v9_0_update_coarse_grain_clock_gating()
4919 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v9_0_update_coarse_grain_clock_gating()
4931 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v9_0_update_coarse_grain_clock_gating()
4934 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v9_0_update_coarse_grain_clock_gating()
4938 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v9_0_update_coarse_grain_clock_gating()
4940 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v9_0_update_coarse_grain_clock_gating()
4945 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v9_0_update_coarse_grain_clock_gating()
4980 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); in gfx_v9_0_update_spm_vmid()
4990 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); in gfx_v9_0_update_spm_vmid()
4992 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); in gfx_v9_0_update_spm_vmid()
5118 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); in gfx_v9_0_get_clockgating_state()
5123 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); in gfx_v9_0_get_clockgating_state()
5132 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); in gfx_v9_0_get_clockgating_state()
5137 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); in gfx_v9_0_get_clockgating_state()
5143 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); in gfx_v9_0_get_clockgating_state()
5167 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); in gfx_v9_0_ring_get_wptr_gfx()
5168 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; in gfx_v9_0_ring_get_wptr_gfx()
5183 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v9_0_ring_set_wptr_gfx()
5184 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v9_0_ring_set_wptr_gfx()
5394 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); in gfx_v9_0_ring_emit_fence_kiq()
5585 WREG32_SOC15(GC, 0, mmSQ_CMD, value); in gfx_v9_0_ring_soft_recovery()
5594 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_gfx_eop_interrupt_state()
5618 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
5621 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
5624 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
5627 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
5664 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_priv_reg_fault_state()
5683 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_priv_inst_fault_state()
5694 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\
5698 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\
5708 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_cp_ecc_error_state()
5717 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_cp_ecc_error_state()
5850 { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT),
5854 { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT),
5858 { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
5862 { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
5866 { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT),
5870 { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT),
5874 { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT),
5878 { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT),
5882 { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
5886 { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
5890 { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT),
5894 { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
5898 { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
5902 { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
5907 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
5912 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
5917 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
5922 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
5927 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
5932 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
5936 { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
5940 { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
5944 { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
5948 { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
5952 { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
5956 { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
5960 { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
5964 { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
5968 { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5972 { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5976 { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5980 { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5984 { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5988 { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5992 { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5996 { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6000 { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6004 { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6008 { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6012 { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6016 { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6020 { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6024 { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6028 { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6032 { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6036 { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6040 { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT),
6044 { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6048 { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6052 { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6056 { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6060 { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6064 { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6068 { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6072 { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
6076 { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
6080 { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
6084 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6088 { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6092 { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6096 { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6100 { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6104 { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6108 { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6112 { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6116 { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6120 { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6124 { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6128 { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6132 { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6136 { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6140 { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6144 { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6148 { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6152 { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6156 { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6160 { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6164 { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6168 { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6172 { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6176 { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6180 { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6184 { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6188 { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6192 { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6196 { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6200 { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6204 { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6208 { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6212 { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6216 { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6220 { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6224 { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6228 { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6232 { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6236 { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6240 { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6244 { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6248 { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6252 { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6256 { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6260 { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6264 { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6268 { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6272 { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6276 { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6280 { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6284 { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6413 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); in gfx_v9_0_query_utc_edc_status()
6414 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); in gfx_v9_0_query_utc_edc_status()
6415 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); in gfx_v9_0_query_utc_edc_status()
6416 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); in gfx_v9_0_query_utc_edc_status()
6417 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); in gfx_v9_0_query_utc_edc_status()
6418 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); in gfx_v9_0_query_utc_edc_status()
6419 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); in gfx_v9_0_query_utc_edc_status()
6420 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); in gfx_v9_0_query_utc_edc_status()
6423 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); in gfx_v9_0_query_utc_edc_status()
6424 data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); in gfx_v9_0_query_utc_edc_status()
6442 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); in gfx_v9_0_query_utc_edc_status()
6443 data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); in gfx_v9_0_query_utc_edc_status()
6463 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); in gfx_v9_0_query_utc_edc_status()
6464 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); in gfx_v9_0_query_utc_edc_status()
6476 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); in gfx_v9_0_query_utc_edc_status()
6477 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); in gfx_v9_0_query_utc_edc_status()
6496 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); in gfx_v9_0_query_utc_edc_status()
6497 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); in gfx_v9_0_query_utc_edc_status()
6498 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); in gfx_v9_0_query_utc_edc_status()
6499 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); in gfx_v9_0_query_utc_edc_status()
6563 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); in gfx_v9_0_reset_ras_error_count()
6566 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); in gfx_v9_0_reset_ras_error_count()
6567 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); in gfx_v9_0_reset_ras_error_count()
6568 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); in gfx_v9_0_reset_ras_error_count()
6569 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); in gfx_v9_0_reset_ras_error_count()
6570 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); in gfx_v9_0_reset_ras_error_count()
6571 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); in gfx_v9_0_reset_ras_error_count()
6572 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); in gfx_v9_0_reset_ras_error_count()
6573 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); in gfx_v9_0_reset_ras_error_count()
6576 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); in gfx_v9_0_reset_ras_error_count()
6577 RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); in gfx_v9_0_reset_ras_error_count()
6581 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); in gfx_v9_0_reset_ras_error_count()
6582 RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); in gfx_v9_0_reset_ras_error_count()
6586 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); in gfx_v9_0_reset_ras_error_count()
6587 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); in gfx_v9_0_reset_ras_error_count()
6591 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); in gfx_v9_0_reset_ras_error_count()
6592 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); in gfx_v9_0_reset_ras_error_count()
6595 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); in gfx_v9_0_reset_ras_error_count()
6596 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); in gfx_v9_0_reset_ras_error_count()
6597 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); in gfx_v9_0_reset_ras_error_count()
6598 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); in gfx_v9_0_reset_ras_error_count()
6919 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); in gfx_v9_0_set_user_cu_inactive_bitmap()
6926 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); in gfx_v9_0_get_cu_active_bitmap()
6927 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); in gfx_v9_0_get_cu_active_bitmap()