Lines Matching refs:GC
35 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; in gfxhub_v1_0_get_mc_fb_offset()
43 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v1_0_setup_vm_pt_regs()
47 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v1_0_setup_vm_pt_regs()
58 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
60 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
63 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
65 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
74 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0); in gfxhub_v1_0_init_system_aperture_regs()
75 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v1_0_init_system_aperture_regs()
76 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v1_0_init_system_aperture_regs()
80 WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v1_0_init_system_aperture_regs()
91 WREG32_SOC15_RLC(GC, 0, in gfxhub_v1_0_init_system_aperture_regs()
97 GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gfxhub_v1_0_init_system_aperture_regs()
103 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in gfxhub_v1_0_init_system_aperture_regs()
105 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, in gfxhub_v1_0_init_system_aperture_regs()
109 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, in gfxhub_v1_0_init_system_aperture_regs()
111 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, in gfxhub_v1_0_init_system_aperture_regs()
114 WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v1_0_init_system_aperture_regs()
124 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_0_init_tlb_regs()
137 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_0_init_tlb_regs()
145 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); in gfxhub_v1_0_init_cache_regs()
154 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp); in gfxhub_v1_0_init_cache_regs()
156 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); in gfxhub_v1_0_init_cache_regs()
159 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp); in gfxhub_v1_0_init_cache_regs()
171 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp); in gfxhub_v1_0_init_cache_regs()
176 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp); in gfxhub_v1_0_init_cache_regs()
183 tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); in gfxhub_v1_0_enable_system_domain()
188 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); in gfxhub_v1_0_enable_system_domain()
193 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, in gfxhub_v1_0_disable_identity_aperture()
195 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, in gfxhub_v1_0_disable_identity_aperture()
198 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, in gfxhub_v1_0_disable_identity_aperture()
200 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, in gfxhub_v1_0_disable_identity_aperture()
203 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); in gfxhub_v1_0_disable_identity_aperture()
204 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); in gfxhub_v1_0_disable_identity_aperture()
223 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i); in gfxhub_v1_0_setup_vmid_config()
249 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
251 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v1_0_setup_vmid_config()
253 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v1_0_setup_vmid_config()
255 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v1_0_setup_vmid_config()
258 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v1_0_setup_vmid_config()
270 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, in gfxhub_v1_0_program_invalidation()
272 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, in gfxhub_v1_0_program_invalidation()
285 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE, in gfxhub_v1_0_gart_enable()
287 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP, in gfxhub_v1_0_gart_enable()
315 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, in gfxhub_v1_0_gart_disable()
319 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_0_gart_disable()
325 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_0_gart_disable()
328 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v1_0_gart_disable()
329 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0); in gfxhub_v1_0_gart_disable()
342 tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v1_0_set_fault_enable_default()
373 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v1_0_set_fault_enable_default()
381 SOC15_REG_OFFSET(GC, 0, in gfxhub_v1_0_init()
384 SOC15_REG_OFFSET(GC, 0, in gfxhub_v1_0_init()
387 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM); in gfxhub_v1_0_init()
389 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ); in gfxhub_v1_0_init()
391 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK); in gfxhub_v1_0_init()
393 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL); in gfxhub_v1_0_init()
395 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS); in gfxhub_v1_0_init()
397 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v1_0_init()