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Searched refs:gpu_read (Results 1 – 17 of 17) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/msm/adreno/
Da6xx_gpu.c20 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
24 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
37 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
38 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), in a6xx_idle()
39 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_idle()
40 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); in a6xx_idle()
235 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); in a6xx_set_hwcg()
485 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); in a6xx_dump()
502 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); in a6xx_recover()
525 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), in a6xx_fault_handler()
[all …]
Da5xx_gpu.c822 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(i))); in a5xx_recover()
829 gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); in a5xx_recover()
867 if (gpu_read(gpu, REG_A5XX_RBBM_STATUS) & ~A5XX_RBBM_STATUS_HI_BUSY) in _a5xx_check_idle()
874 return !(gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS) & in _a5xx_check_idle()
895 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_idle()
896 gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS), in a5xx_idle()
897 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_idle()
898 gpu_read(gpu, REG_A5XX_CP_RB_WPTR)); in a5xx_idle()
910 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(4)), in a5xx_fault_handler()
911 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(5)), in a5xx_fault_handler()
[all …]
Da4xx_gpu.c237 val = gpu_read(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ); in a4xx_hw_init()
308 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a4xx_recover()
316 gpu_read(gpu, REG_A4XX_RBBM_SW_RESET_CMD); in a4xx_recover()
345 if (spin_until(!(gpu_read(gpu, REG_A4XX_RBBM_STATUS) & in a4xx_idle()
359 status = gpu_read(gpu, REG_A4XX_RBBM_INT_0_STATUS); in a4xx_irq()
363 uint32_t reg = gpu_read(gpu, REG_A4XX_CP_PROTECT_STATUS); in a4xx_irq()
467 state->rbbm_status = gpu_read(gpu, REG_A4XX_RBBM_STATUS); in a4xx_gpu_state_get()
486 gpu_read(gpu, REG_A4XX_RBBM_STATUS)); in a4xx_dump()
504 reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS); in a4xx_pm_resume()
Da5xx_debugfs.c30 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print()
45 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print()
60 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print()
77 val[j] = gpu_read(gpu, REG_A5XX_CP_ROQ_DBG_DATA); in roq_print()
Da3xx_gpu.c310 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a3xx_recover()
318 gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD); in a3xx_recover()
347 if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) & in a3xx_idle()
362 status = gpu_read(gpu, REG_A3XX_RBBM_INT_0_STATUS); in a3xx_irq()
418 gpu_read(gpu, REG_A3XX_RBBM_STATUS)); in a3xx_dump()
431 state->rbbm_status = gpu_read(gpu, REG_A3XX_RBBM_STATUS); in a3xx_gpu_state_get()
Da5xx_gpu.h144 if ((gpu_read(gpu, reg) & mask) == value) in spin_usecs()
Da5xx_preempt.c188 status = gpu_read(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL); in a5xx_preempt_irq()
Dadreno_gpu.h325 val = gpu_read(&gpu->base, reg - 1); in adreno_gpu_read()
Dadreno_gpu.c433 state->registers[pos++] = gpu_read(gpu, addr); in adreno_gpu_state_get()
606 uint32_t val = gpu_read(gpu, addr); in adreno_dump()
/Linux-v4.19/drivers/gpu/drm/etnaviv/
Detnaviv_gpu.c166 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs()
167 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); in etnaviv_hw_specs()
168 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); in etnaviv_hw_specs()
169 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); in etnaviv_hw_specs()
313 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); in etnaviv_hw_identify()
322 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); in etnaviv_hw_identify()
323 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); in etnaviv_hw_identify()
338 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); in etnaviv_hw_identify()
339 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); in etnaviv_hw_identify()
373 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); in etnaviv_hw_identify()
[all …]
Detnaviv_perfmon.c42 return gpu_read(gpu, signal->data); in simple_reg_read()
51 return gpu_read(gpu, domain->profile_read); in perf_reg_read()
58 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_reg_read()
67 value += gpu_read(gpu, domain->profile_read); in pipe_reg_read()
Detnaviv_iommu_v2.c235 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
255 if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE) in etnaviv_iommuv2_restore_sec()
Detnaviv_gpu.h159 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() function
Detnaviv_sched.c104 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in etnaviv_sched_timedout_job()
Detnaviv_dump.c87 reg->value = gpu_read(gpu, etnaviv_dump_registers[i]); in etnaviv_core_dump_registers()
/Linux-v4.19/drivers/gpu/drm/msm/
Dmsm_gpu.h221 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) in gpu_read() function
228 uint32_t val = gpu_read(gpu, reg); in gpu_rmw()
Dmsm_gpu.c563 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg); in update_hw_cntrs()