166 		specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);  in etnaviv_hw_specs()
167 		specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);  in etnaviv_hw_specs()
168 		specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);  in etnaviv_hw_specs()
169 		specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);  in etnaviv_hw_specs()
313 	chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);  in etnaviv_hw_identify()
322 		gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);  in etnaviv_hw_identify()
323 		gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);  in etnaviv_hw_identify()
338 			u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);  in etnaviv_hw_identify()
339 			u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);  in etnaviv_hw_identify()
373 	gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);  in etnaviv_hw_identify()
396 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);  in etnaviv_hw_identify()
401 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);  in etnaviv_hw_identify()
403 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);  in etnaviv_hw_identify()
405 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);  in etnaviv_hw_identify()
407 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);  in etnaviv_hw_identify()
409 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);  in etnaviv_hw_identify()
446 		u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in etnaviv_gpu_update_clock()
494 		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_hw_reset()
503 		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in etnaviv_hw_reset()
521 		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_hw_reset()
522 		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in etnaviv_hw_reset()
543 	ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);  in etnaviv_gpu_enable_mlcg()
553 	pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);  in etnaviv_gpu_enable_mlcg()
623 		pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);  in etnaviv_gpu_setup_pulse_eater()
636 	    gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {  in etnaviv_gpu_hw_init()
639 		mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;  in etnaviv_gpu_hw_init()
662 		u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);  in etnaviv_gpu_hw_init()
671 		u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);  in etnaviv_gpu_hw_init()
823 	debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);  in verify_dma()
824 	debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);  in verify_dma()
827 		debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);  in verify_dma()
828 		debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);  in verify_dma()
850 	dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);  in etnaviv_gpu_debugfs()
851 	dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);  in etnaviv_gpu_debugfs()
852 	axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);  in etnaviv_gpu_debugfs()
853 	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_gpu_debugfs()
940 		u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);  in etnaviv_gpu_debugfs()
941 		u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);  in etnaviv_gpu_debugfs()
942 		u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);  in etnaviv_gpu_debugfs()
1229 	val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);  in sync_point_perfmon_sample_pre()
1234 	val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in sync_point_perfmon_sample_pre()
1257 	val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in sync_point_perfmon_sample_post()
1262 	val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);  in sync_point_perfmon_sample_post()
1341 	u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);  in sync_point_worker()
1361 	status = gpu_read(gpu, status_reg);  in dump_mmu_fault()
1376 				    gpu_read(gpu, address_reg));  in dump_mmu_fault()
1385 	u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);  in irq_handler()
1505 		u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_gpu_wait_idle()
1815 	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;  in etnaviv_gpu_rpm_suspend()