20 	if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) &  in _a6xx_check_idle()
24 	return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) &  in _a6xx_check_idle()
37 			gpu_read(gpu, REG_A6XX_RBBM_STATUS),  in a6xx_idle()
38 			gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS),  in a6xx_idle()
39 			gpu_read(gpu, REG_A6XX_CP_RB_RPTR),  in a6xx_idle()
40 			gpu_read(gpu, REG_A6XX_CP_RB_WPTR));  in a6xx_idle()
235 	val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);  in a6xx_set_hwcg()
485 			gpu_read(gpu, REG_A6XX_RBBM_STATUS));  in a6xx_dump()
502 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i)));  in a6xx_recover()
525 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),  in a6xx_fault_handler()
526 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),  in a6xx_fault_handler()
527 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),  in a6xx_fault_handler()
528 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));  in a6xx_fault_handler()
535 	u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS);  in a6xx_cp_hw_err_irq()
541 		val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA);  in a6xx_cp_hw_err_irq()
553 			gpu_read(gpu, REG_A6XX_CP_HW_FAULT));  in a6xx_cp_hw_err_irq()
556 		u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS);  in a6xx_cp_hw_err_irq()
592 		gpu_read(gpu, REG_A6XX_RBBM_STATUS),  in a6xx_fault_detect_irq()
593 		gpu_read(gpu, REG_A6XX_CP_RB_RPTR),  in a6xx_fault_detect_irq()
594 		gpu_read(gpu, REG_A6XX_CP_RB_WPTR),  in a6xx_fault_detect_irq()
596 		gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),  in a6xx_fault_detect_irq()
598 		gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));  in a6xx_fault_detect_irq()
608 	u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS);  in a6xx_irq()
702 	spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 0xf) == 0xf);  in a6xx_pm_suspend()