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/Linux-v4.19/Documentation/devicetree/bindings/sound/
Dbrcm,cygnus-audio.txt13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
40 assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
41 assigned-clock-rates = <1769470191>,
Dmt2701-afe-pcm.txt47 - assigned-clocks: list of input clocks and dividers for the audio system.
49 - assigned-clocks-parents: parent of input clocks of assigned clocks.
50 - assigned-clock-rates: list of clock frequencies of assigned clocks.
138 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
142 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
144 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
/Linux-v4.19/arch/arm/boot/dts/
Dexynos4412-odroid-common.dtsi140 assigned-clocks = <&clock CLK_FOUT_EPLL>;
141 assigned-clock-rates = <45158401>;
145 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
151 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
154 assigned-clock-rates = <0>, <0>,
199 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
201 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
202 assigned-clock-rates = <0>, <176000000>;
207 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
209 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
[all …]
Dexynos5422-odroidxu4.dts36 assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>,
46 assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>,
53 assigned-clock-rates = <0>,
74 assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>,
76 assigned-clock-rates = <(196608000 / 256)>,
Dexynos5422-odroidxu3-audio.dtsi29 assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>,
39 assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>,
46 assigned-clock-rates = <0>,
66 assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>,
68 assigned-clock-rates = <(196608000 / 256)>,
Dimx7d-cl-som-imx7.dts42 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
44 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
45 assigned-clock-rates = <0>, <100000000>;
68 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
70 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
71 assigned-clock-rates = <0>, <100000000>;
190 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
191 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
205 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
206 assigned-clock-rates = <400000000>;
Dimx7d-nitrogen7.dts109 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
111 assigned-clock-parents = <&clks IMX7D_CKIL>;
112 assigned-clock-rates = <0>, <32768>;
122 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
124 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
125 assigned-clock-rates = <0>, <100000000>;
313 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
314 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
321 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
322 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
[all …]
Dexynos4412-itop-elite.dts130 assigned-clocks = <&clock CLK_MOUT_CAM0>;
131 assigned-clock-parents = <&clock CLK_XUSBXTI>;
135 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
139 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
141 assigned-clock-rates = <0>, <0>, <112896000>, <11289600>;
164 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
166 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
167 assigned-clock-rates = <0>, <176000000>;
Dimx7d-pico-pi.dts66 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
68 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
69 assigned-clock-rates = <0>, <100000000>;
107 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
109 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
110 assigned-clock-rates = <0>, <24576000>;
117 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
118 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
Dimx7s-warp.dts112 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
113 assigned-clock-rates = <884736000>;
246 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
248 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
249 assigned-clock-rates = <0>, <36864000>;
256 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
257 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
264 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
265 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
273 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
[all …]
Dexynos4210-trats.dts208 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
210 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
211 assigned-clock-rates = <0>, <160000000>;
216 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
218 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
219 assigned-clock-rates = <0>, <160000000>;
224 assigned-clocks = <&clock CLK_MOUT_FIMC2>,
226 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
227 assigned-clock-rates = <0>, <160000000>;
232 assigned-clocks = <&clock CLK_MOUT_FIMC3>,
[all …]
Dstih407.dtsi19 assigned-clocks = <&clk_s_d2_quadfs 0>,
31 assigned-clock-parents = <0>,
43 assigned-clock-rates = <297000000>,
91 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
98 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
Dimx6ull-colibri-wifi.dtsi40 assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
41 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
42 assigned-clock-rates = <0>, <198000000>;
Ddra76x.dtsi61 assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
62 assigned-clock-rates = <80000000>;
72 assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
73 assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
Dexynos4210-universal_c210.dts205 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
207 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
208 assigned-clock-rates = <0>, <160000000>;
213 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
215 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
216 assigned-clock-rates = <0>, <160000000>;
221 assigned-clocks = <&clock CLK_MOUT_FIMC2>,
223 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
224 assigned-clock-rates = <0>, <160000000>;
229 assigned-clocks = <&clock CLK_MOUT_FIMC3>,
[all …]
/Linux-v4.19/Documentation/devicetree/bindings/display/msm/
Ddpu.txt33 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
34 - assigned-clock-rates: list of clock frequencies sorted in the same order as
35 the assigned-clocks property.
65 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
66 - assigned-clock-rates: list of clock frequencies sorted in the same order as
67 the assigned-clocks property.
82 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
83 assigned-clock-rates = <300000000>;
106 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
108 assigned-clock-rates = <0 0 300000000 19200000>;
/Linux-v4.19/arch/mips/boot/dts/img/
Dpistachio.dtsi54 assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
56 assigned-clock-rates = <100000000>, <33333334>;
72 assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
74 assigned-clock-rates = <100000000>, <33333334>;
90 assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
92 assigned-clock-rates = <100000000>, <33333334>;
108 assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
110 assigned-clock-rates = <100000000>, <33333334>;
144 assigned-clocks = <&clk_core CLK_I2S_DIV>;
145 assigned-clock-rates = <12288000>;
[all …]
/Linux-v4.19/drivers/s390/char/
Dsclp_cmd.c241 u16 assigned; member
264 for (i = 0; i < sccb->assigned; i++) { in sclp_attach_storage()
425 static void __init insert_increment(u16 rn, int standby, int assigned) in insert_increment() argument
439 if (assigned && incr->rn > rn) in insert_increment()
441 if (!assigned && incr->rn - last_rn > 1) in insert_increment()
446 if (!assigned) in insert_increment()
466 u16 assigned; member
487 int i, id, assigned, rc; in sclp_detect_standby_memory() local
497 assigned = 0; in sclp_detect_standby_memory()
507 for (i = 0; i < sccb->assigned; i++) { in sclp_detect_standby_memory()
[all …]
/Linux-v4.19/Documentation/devicetree/bindings/rtc/
Dst,stm32-rtc.txt25 - assigned-clocks: reference to the rtc_ck clock entry.
26 - assigned-clock-parents: phandle of the new parent clock of rtc_ck.
34 assigned-clocks = <&rcc 1 CLK_RTC>;
35 assigned-clock-parents = <&rcc 1 CLK_LSE>;
46 assigned-clocks = <&rcc RTC_CK>;
47 assigned-clock-parents = <&rcc LSE_CK>;
/Linux-v4.19/Documentation/devicetree/bindings/phy/
Dphy-rockchip-typec.txt11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
46 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
47 assigned-clock-rates = <50000000>;
70 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
71 assigned-clock-rates = <50000000>;
/Linux-v4.19/Documentation/devicetree/bindings/ata/
Dqcom-sata.txt22 - assigned-clocks : Shall be:
25 - assigned-clock-rates : Shall be:
43 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
44 assigned-clock-rates = <100000000>, <100000000>;
/Linux-v4.19/Documentation/devicetree/bindings/display/hisilicon/
Dhisi-ade.txt20 - assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
22 - assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
54 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
56 assigned-clock-rates = <360000000>, <288000000>;
/Linux-v4.19/arch/arm64/boot/dts/exynos/
Dexynos5433-tm2e.dts20 * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
24 assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
37 assigned-clock-parents = <0>, <0>,
49 assigned-clock-rates = <278000000>, <400000000>;
Dexynos5433-tm2.dts20 * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
24 assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
37 assigned-clock-parents = <0>, <0>,
49 assigned-clock-rates = <250000000>, <400000000>;
/Linux-v4.19/Documentation/devicetree/bindings/arm/
Dsp810.txt27 - assigned-clocks: from the common clock binding;
31 - assigned-clock-parents: from the common clock binding;
43 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
44 …assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz…

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