1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Hardkernel Odroid XU4 board device tree source 4 * 5 * Copyright (c) 2015 Krzysztof Kozlowski 6 * Copyright (c) 2014 Collabora Ltd. 7 * Copyright (c) 2013-2015 Samsung Electronics Co., Ltd. 8 * http://www.samsung.com 9 */ 10 11/dts-v1/; 12#include <dt-bindings/sound/samsung-i2s.h> 13#include "exynos5422-odroidxu3-common.dtsi" 14 15/ { 16 model = "Hardkernel Odroid XU4"; 17 compatible = "hardkernel,odroid-xu4", "samsung,exynos5800", \ 18 "samsung,exynos5"; 19 20 pwmleds { 21 compatible = "pwm-leds"; 22 23 blueled { 24 label = "blue:heartbeat"; 25 pwms = <&pwm 2 2000000 0>; 26 pwm-names = "pwm2"; 27 max_brightness = <255>; 28 linux,default-trigger = "heartbeat"; 29 }; 30 }; 31 32 sound: sound { 33 compatible = "samsung,odroid-xu3-audio"; 34 model = "Odroid-XU4"; 35 36 assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>, 37 <&clock CLK_MOUT_EPLL>, 38 <&clock CLK_MOUT_MAU_EPLL>, 39 <&clock CLK_MOUT_USER_MAU_EPLL>, 40 <&clock_audss EXYNOS_MOUT_AUDSS>, 41 <&clock_audss EXYNOS_MOUT_I2S>, 42 <&clock_audss EXYNOS_DOUT_SRP>, 43 <&clock_audss EXYNOS_DOUT_AUD_BUS>, 44 <&clock_audss EXYNOS_DOUT_I2S>; 45 46 assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>, 47 <&clock CLK_FOUT_EPLL>, 48 <&clock CLK_MOUT_EPLL>, 49 <&clock CLK_MOUT_MAU_EPLL>, 50 <&clock CLK_MAU_EPLL>, 51 <&clock_audss EXYNOS_MOUT_AUDSS>; 52 53 assigned-clock-rates = <0>, 54 <0>, 55 <0>, 56 <0>, 57 <0>, 58 <0>, 59 <196608001>, 60 <(196608002 / 2)>, 61 <196608000>; 62 63 cpu { 64 sound-dai = <&i2s0 0>; 65 }; 66 67 codec { 68 sound-dai = <&hdmi>; 69 }; 70 }; 71}; 72 73&clock_audss { 74 assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>, 75 <&clock CLK_FOUT_EPLL>; 76 assigned-clock-rates = <(196608000 / 256)>, 77 <196608000>; 78}; 79 80&i2s0 { 81 status = "okay"; 82}; 83 84&pwm { 85 /* 86 * PWM 0 -- fan 87 * PWM 2 -- Blue LED 88 */ 89 pinctrl-0 = <&pwm0_out &pwm2_out>; 90 pinctrl-names = "default"; 91 samsung,pwm-outputs = <0>, <2>; 92 status = "okay"; 93}; 94 95&usbdrd_dwc3_1 { 96 dr_mode = "host"; 97}; 98