1Qualcomm Technologies, Inc. DPU KMS
2
3Description:
4
5Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
6sub-blocks like DPU display controller, DSI and DP interfaces etc.
7The DPU display controller is found in SDM845 SoC.
8
9MDSS:
10Required properties:
11- compatible: "qcom,sdm845-mdss"
12- reg: physical base address and length of contoller's registers.
13- reg-names: register region names. The following region is required:
14  * "mdss"
15- power-domains: a power domain consumer specifier according to
16  Documentation/devicetree/bindings/power/power_domain.txt
17- clocks: list of clock specifiers for clocks needed by the device.
18- clock-names: device clock names, must be in same order as clocks property.
19  The following clocks are required:
20  * "iface"
21  * "bus"
22  * "core"
23- interrupts: interrupt signal from MDSS.
24- interrupt-controller: identifies the node as an interrupt controller.
25- #interrupt-cells: specifies the number of cells needed to encode an interrupt
26  source, should be 1.
27- iommus: phandle of iommu device node.
28- #address-cells: number of address cells for the MDSS children. Should be 1.
29- #size-cells: Should be 1.
30- ranges: parent bus address space is the same as the child bus address space.
31
32Optional properties:
33- assigned-clocks: list of clock specifiers for clocks needing rate assignment
34- assigned-clock-rates: list of clock frequencies sorted in the same order as
35  the assigned-clocks property.
36
37MDP:
38Required properties:
39- compatible: "qcom,sdm845-dpu"
40- reg: physical base address and length of controller's registers.
41- reg-names : register region names. The following region is required:
42  * "mdp"
43  * "vbif"
44- clocks: list of clock specifiers for clocks needed by the device.
45- clock-names: device clock names, must be in same order as clocks property.
46  The following clocks are required.
47  * "bus"
48  * "iface"
49  * "core"
50  * "vsync"
51- interrupts: interrupt line from DPU to MDSS.
52- ports: contains the list of output ports from DPU device. These ports connect
53  to interfaces that are external to the DPU hardware, such as DSI, DP etc.
54
55  Each output port contains an endpoint that describes how it is connected to an
56  external interface. These are described by the standard properties documented
57  here:
58	Documentation/devicetree/bindings/graph.txt
59	Documentation/devicetree/bindings/media/video-interfaces.txt
60
61	Port 0 -> DPU_INTF1 (DSI1)
62	Port 1 -> DPU_INTF2 (DSI2)
63
64Optional properties:
65- assigned-clocks: list of clock specifiers for clocks needing rate assignment
66- assigned-clock-rates: list of clock frequencies sorted in the same order as
67  the assigned-clocks property.
68
69Example:
70
71	mdss: mdss@ae00000 {
72		compatible = "qcom,sdm845-mdss";
73		reg = <0xae00000 0x1000>;
74		reg-names = "mdss";
75
76		power-domains = <&clock_dispcc 0>;
77
78		clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
79			 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
80		clock-names = "iface", "bus", "core";
81
82		assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
83		assigned-clock-rates = <300000000>;
84
85		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
86		interrupt-controller;
87		#interrupt-cells = <1>;
88
89		iommus = <&apps_iommu 0>;
90
91		#address-cells = <2>;
92		#size-cells = <1>;
93		ranges = <0 0 0xae00000 0xb2008>;
94
95		mdss_mdp: mdp@ae01000 {
96			compatible = "qcom,sdm845-dpu";
97			reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>;
98			reg-names = "mdp", "vbif";
99
100			clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
101				 <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
102				 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
103				 <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
104			clock-names = "iface", "bus", "core", "vsync";
105
106			assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
107					  <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
108			assigned-clock-rates = <0 0 300000000 19200000>;
109
110			interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
111
112			ports {
113				#address-cells = <1>;
114				#size-cells = <0>;
115
116				port@0 {
117					reg = <0>;
118					dpu_intf1_out: endpoint {
119						remote-endpoint = <&dsi0_in>;
120					};
121				};
122
123				port@1 {
124					reg = <1>;
125					dpu_intf2_out: endpoint {
126						remote-endpoint = <&dsi1_in>;
127					};
128				};
129			};
130		};
131	};
132