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Searched refs:CLK_SET_RATE_PARENT (Results 1 – 25 of 213) sorted by relevance

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/Linux-v4.19/drivers/clk/hisilicon/
Dclk-hi3660.c57 CLK_SET_RATE_PARENT, 0x0, 0, 0, },
59 CLK_SET_RATE_PARENT, 0x0, 21, 0, },
61 CLK_SET_RATE_PARENT, 0x0, 30, 0, },
63 CLK_SET_RATE_PARENT, 0x0, 31, 0, },
65 CLK_SET_RATE_PARENT, 0x10, 0, 0, },
67 CLK_SET_RATE_PARENT, 0x10, 1, 0, },
69 CLK_SET_RATE_PARENT, 0x10, 2, 0, },
71 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
73 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
75 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
[all …]
Dclk-hi6220.c58 …{ HI6220_WDT0_PCLK, "wdt0_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12,…
59 …{ HI6220_WDT1_PCLK, "wdt1_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13,…
60 …{ HI6220_WDT2_PCLK, "wdt2_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14,…
61 …{ HI6220_TIMER0_PCLK, "timer0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 15,…
62 …{ HI6220_TIMER1_PCLK, "timer1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 16,…
63 …{ HI6220_TIMER2_PCLK, "timer2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 17,…
64 …{ HI6220_TIMER3_PCLK, "timer3_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 18,…
65 …{ HI6220_TIMER4_PCLK, "timer4_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 19,…
66 …{ HI6220_TIMER5_PCLK, "timer5_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 20,…
67 …{ HI6220_TIMER6_PCLK, "timer6_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 21,…
[all …]
Dclk-hi3620.c100 …{ HI3620_TIMER0_MUX, "timer0_mux", timer0_mux_p, ARRAY_SIZE(timer0_mux_p), CLK_SET_RATE_PARENT, 0,…
101 …{ HI3620_TIMER1_MUX, "timer1_mux", timer1_mux_p, ARRAY_SIZE(timer1_mux_p), CLK_SET_RATE_PARENT, 0,…
102 …{ HI3620_TIMER2_MUX, "timer2_mux", timer2_mux_p, ARRAY_SIZE(timer2_mux_p), CLK_SET_RATE_PARENT, 0,…
103 …{ HI3620_TIMER3_MUX, "timer3_mux", timer3_mux_p, ARRAY_SIZE(timer3_mux_p), CLK_SET_RATE_PARENT, 0,…
104 …{ HI3620_TIMER4_MUX, "timer4_mux", timer4_mux_p, ARRAY_SIZE(timer4_mux_p), CLK_SET_RATE_PARENT, 0x…
105 …{ HI3620_TIMER5_MUX, "timer5_mux", timer5_mux_p, ARRAY_SIZE(timer5_mux_p), CLK_SET_RATE_PARENT, 0x…
106 …{ HI3620_TIMER6_MUX, "timer6_mux", timer6_mux_p, ARRAY_SIZE(timer6_mux_p), CLK_SET_RATE_PARENT, 0x…
107 …{ HI3620_TIMER7_MUX, "timer7_mux", timer7_mux_p, ARRAY_SIZE(timer7_mux_p), CLK_SET_RATE_PARENT, 0x…
108 …{ HI3620_TIMER8_MUX, "timer8_mux", timer8_mux_p, ARRAY_SIZE(timer8_mux_p), CLK_SET_RATE_PARENT, 0x…
109 …{ HI3620_TIMER9_MUX, "timer9_mux", timer9_mux_p, ARRAY_SIZE(timer9_mux_p), CLK_SET_RATE_PARENT, 0x…
[all …]
Dcrg-hi3798cv200.c88 CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
91 CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, },
94 CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, },
96 ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
105 CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees,
108 CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees,
115 CLK_SET_RATE_PARENT, 0x68, 4, 0, },
118 CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
120 CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
122 CLK_SET_RATE_PARENT, 0x6C, 12, 0, },
[all …]
Dclk-hix5hd2.c63 CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, },
65 CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio_mux_table, },
67 CLK_SET_RATE_PARENT, 0x9c, 8, 2, 0, sdio_mux_table, },
70 CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, },
76 CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
78 CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, },
81 CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
83 CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
85 CLK_SET_RATE_PARENT, 0x9c, 4, CLK_GATE_SET_TO_DISABLE, },
88 CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
[all …]
Dcrg-hi3516cv300.c82 CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, },
84 CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
86 CLK_SET_RATE_PARENT, 0xc4, 4, 2, 0, mmc_mux_table, },
88 CLK_SET_RATE_PARENT, 0xc4, 12, 2, 0, mmc_mux_table, },
90 CLK_SET_RATE_PARENT, 0xc4, 20, 2, 0, mmc2_mux_table, },
92 CLK_SET_RATE_PARENT, 0xc8, 4, 2, 0, mmc_mux_table, },
94 CLK_SET_RATE_PARENT, 0x38, 2, 2, 0, pwm_mux_table, },
99 { HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
101 { HI3516CV300_UART1_CLK, "clk_uart1", "uart_mux", CLK_SET_RATE_PARENT,
103 { HI3516CV300_UART2_CLK, "clk_uart2", "uart_mux", CLK_SET_RATE_PARENT,
[all …]
Dclk-hi3519.c64 CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
69 CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
71 CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
73 CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
75 CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
77 CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
79 CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
81 CLK_SET_RATE_PARENT, 0xe4, 16, 0, },
83 CLK_SET_RATE_PARENT, 0xe4, 17, 0, },
85 CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
/Linux-v4.19/drivers/clk/mmp/
Dclk-of-mmp2.c118 CLK_SET_RATE_PARENT, in mmp2_pll_init()
142 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
143 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
144 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2…
145 …{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3…
146 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
147 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
148 …{0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4,…
149 …{0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4,…
150 …{0, "timer_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIM…
[all …]
Dclk-of-pxa168.c106 CLK_SET_RATE_PARENT, in pxa168_pll_init()
131 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
132 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
133 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2…
134 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
135 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
136 …{0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4,…
137 …{0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4,…
138 …{0, "ssp4_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP4, 4,…
139 …{0, "timer_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIM…
[all …]
Dclk-of-pxa910.c106 CLK_SET_RATE_PARENT, in pxa910_pll_init()
129 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
130 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
131 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
132 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
133 …{0, "timer0_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TI…
134 …{0, "timer1_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TI…
138 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART…
142 …{PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, …
143 …{PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_l…
[all …]
Dclk-of-pxa1928.c81 CLK_SET_RATE_PARENT, in pxa1928_pll_init()
100 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
101 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
102 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
103 …{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
104 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_S…
105 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_S…
109 …{PXA1928_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0…
110 …{PXA1928_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0…
111 …{PXA1928_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0…
[all …]
Dclk-mmp2.c119 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
123 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
127 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
131 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
135 CLK_SET_RATE_PARENT, 1, 5); in mmp2_clk_init()
139 CLK_SET_RATE_PARENT, 1, 3); in mmp2_clk_init()
143 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
147 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
151 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
155 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
[all …]
Dclk-pxa168.c105 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
109 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
113 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
117 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
121 CLK_SET_RATE_PARENT, 1, 3); in pxa168_clk_init()
125 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
129 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
133 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
137 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
141 CLK_SET_RATE_PARENT, 1, 13); in pxa168_clk_init()
[all …]
Dclk-pxa910.c110 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
114 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
118 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
122 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
126 CLK_SET_RATE_PARENT, 1, 3); in pxa910_clk_init()
130 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
134 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
138 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
142 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
146 CLK_SET_RATE_PARENT, 1, 13); in pxa910_clk_init()
[all …]
/Linux-v4.19/drivers/clk/zte/
Dclk-zx296718.c402 FFACTOR(0, "clk1600m", "pll_cpu", 1, 1, CLK_SET_RATE_PARENT),
403 FFACTOR(0, "clk800m", "pll_cpu", 1, 2, CLK_SET_RATE_PARENT),
436 FFACTOR(0, "clk_vga", "pll_vga", 1, 1, CLK_SET_RATE_PARENT),
451 FFACTOR(0, "emmc_mux_div2", "emmc_mux", 1, 2, CLK_SET_RATE_PARENT),
467 MUX_F(0, "a53_mux", a53_coreclk_p, TOP_CLK_MUX0, 0, 3, CLK_SET_RATE_PARENT, 0),
476 MUX_F(0, "wdt_mux", wdt_ares_p, TOP_CLK_MUX9, 8, 1, CLK_SET_RATE_PARENT, 0),
485 MUX_F(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7, 4, 3, CLK_SET_RATE_PARENT, 0),
486 MUX_F(0, "vou_aux_w_mux", vou_aux_wclk_p, TOP_CLK_MUX7, 8, 3, CLK_SET_RATE_PARENT, 0),
497 …GATE(CPU_DBG_GATE, "dbg_wclk", "dbg_mux", TOP_CLK_GATE0, 4, CLK_SET_RATE_PARENT, …
498 …GATE(A72_GATE, "a72_coreclk", "a72_mux", TOP_CLK_GATE0, 3, CLK_SET_RATE_PARENT, …
[all …]
/Linux-v4.19/drivers/clk/qcom/
Dgcc-ipq8074.c434 .flags = CLK_SET_RATE_PARENT,
481 .flags = CLK_SET_RATE_PARENT,
514 .flags = CLK_SET_RATE_PARENT,
548 .flags = CLK_SET_RATE_PARENT,
562 .flags = CLK_SET_RATE_PARENT,
595 .flags = CLK_SET_RATE_PARENT,
627 .flags = CLK_SET_RATE_PARENT,
662 .flags = CLK_SET_RATE_PARENT,
1015 .flags = CLK_SET_RATE_PARENT,
1058 .flags = CLK_SET_RATE_PARENT,
[all …]
Dmmcc-msm8996.c292 .flags = CLK_SET_RATE_PARENT,
322 .flags = CLK_SET_RATE_PARENT,
348 .flags = CLK_SET_RATE_PARENT,
374 .flags = CLK_SET_RATE_PARENT,
400 .flags = CLK_SET_RATE_PARENT,
426 .flags = CLK_SET_RATE_PARENT,
452 .flags = CLK_SET_RATE_PARENT,
478 .flags = CLK_SET_RATE_PARENT,
548 .flags = CLK_SET_RATE_PARENT,
661 .flags = CLK_SET_RATE_PARENT,
[all …]
Dmmcc-apq8084.c583 .flags = CLK_SET_RATE_PARENT,
597 .flags = CLK_SET_RATE_PARENT,
848 .flags = CLK_SET_RATE_PARENT,
861 .flags = CLK_SET_RATE_PARENT,
899 .flags = CLK_SET_RATE_PARENT,
968 .flags = CLK_SET_RATE_PARENT,
1117 .flags = CLK_SET_RATE_PARENT,
1134 .flags = CLK_SET_RATE_PARENT,
1151 .flags = CLK_SET_RATE_PARENT,
1168 .flags = CLK_SET_RATE_PARENT,
[all …]
Dgcc-msm8996.c1293 .flags = CLK_SET_RATE_PARENT,
1308 .flags = CLK_SET_RATE_PARENT,
1323 .flags = CLK_SET_RATE_PARENT,
1338 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1351 .flags = CLK_SET_RATE_PARENT,
1366 .flags = CLK_SET_RATE_PARENT,
1381 .flags = CLK_SET_RATE_PARENT,
1396 .flags = CLK_SET_RATE_PARENT,
1411 .flags = CLK_SET_RATE_PARENT,
1427 .flags = CLK_SET_RATE_PARENT,
[all …]
Dgcc-msm8916.c990 .flags = CLK_SET_RATE_PARENT,
1047 .flags = CLK_SET_RATE_PARENT,
1236 .flags = CLK_SET_RATE_PARENT,
1253 .flags = CLK_SET_RATE_PARENT,
1315 .flags = CLK_SET_RATE_PARENT,
1346 .flags = CLK_SET_RATE_PARENT,
1377 .flags = CLK_SET_RATE_PARENT,
1412 .flags = CLK_SET_RATE_PARENT,
1429 .flags = CLK_SET_RATE_PARENT,
1468 .flags = CLK_SET_RATE_PARENT,
[all …]
Dmmcc-msm8974.c534 .flags = CLK_SET_RATE_PARENT,
548 .flags = CLK_SET_RATE_PARENT,
781 .flags = CLK_SET_RATE_PARENT,
795 .flags = CLK_SET_RATE_PARENT,
833 .flags = CLK_SET_RATE_PARENT,
902 .flags = CLK_SET_RATE_PARENT,
969 .flags = CLK_SET_RATE_PARENT,
1002 .flags = CLK_SET_RATE_PARENT,
1019 .flags = CLK_SET_RATE_PARENT,
1036 .flags = CLK_SET_RATE_PARENT,
[all …]
Dgcc-msm8994.c1079 .flags = CLK_SET_RATE_PARENT,
1097 .flags = CLK_SET_RATE_PARENT,
1115 .flags = CLK_SET_RATE_PARENT,
1133 .flags = CLK_SET_RATE_PARENT,
1151 .flags = CLK_SET_RATE_PARENT,
1169 .flags = CLK_SET_RATE_PARENT,
1187 .flags = CLK_SET_RATE_PARENT,
1205 .flags = CLK_SET_RATE_PARENT,
1223 .flags = CLK_SET_RATE_PARENT,
1241 .flags = CLK_SET_RATE_PARENT,
[all …]
/Linux-v4.19/drivers/clk/rockchip/
Dclk-px30.c212 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
216 MUX(0, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
220 MUX(0, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
224 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
228 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
232 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
236 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
240 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
244 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
248 MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
[all …]
/Linux-v4.19/drivers/clk/samsung/
Dclk-exynos5250.c298 CLK_SET_RATE_PARENT, 0),
421 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
435 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
438 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
442 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
445 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
454 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
457 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
461 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
494 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-exynos5410.c150 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
152 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
154 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
176 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
178 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
180 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
189 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
191 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
193 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
195 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
[all …]

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