Lines Matching refs:CLK_SET_RATE_PARENT
88 CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
91 CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, },
94 CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, },
96 ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
105 CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees,
108 CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees,
115 CLK_SET_RATE_PARENT, 0x68, 4, 0, },
118 CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
120 CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
122 CLK_SET_RATE_PARENT, 0x6C, 12, 0, },
124 CLK_SET_RATE_PARENT, 0x6C, 16, 0, },
126 CLK_SET_RATE_PARENT, 0x6C, 20, 0, },
129 CLK_SET_RATE_PARENT, 0x70, 0, 0, },
132 CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
134 CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
137 CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
139 CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
142 CLK_SET_RATE_PARENT, 0x18c, 0, 0, },
144 CLK_SET_RATE_PARENT, 0x18c, 1, 0, },
146 CLK_SET_RATE_PARENT, 0x18c, 2, 0, },
148 CLK_SET_RATE_PARENT, 0x18c, 3, 0, },
151 CLK_SET_RATE_PARENT, 0xcc, 5, 0, },
153 CLK_SET_RATE_PARENT, 0xcc, 0, 0, },
155 CLK_SET_RATE_PARENT, 0xcc, 1, 0, },
157 CLK_SET_RATE_PARENT, 0xcc, 2, 0, },
159 CLK_SET_RATE_PARENT, 0xcc, 3, 0, },
161 CLK_SET_RATE_PARENT, 0xcc, 24, 0, },
163 CLK_SET_RATE_PARENT, 0xcc, 4, 0, },
165 CLK_SET_RATE_PARENT, 0xcc, 25, 0, },
168 CLK_SET_RATE_PARENT, 0x188, 0, 0, },
171 CLK_SET_RATE_PARENT, 0x188, 8, 0, },
174 CLK_SET_RATE_PARENT, 0xb8, 0, 0, },
176 CLK_SET_RATE_PARENT, 0xb8, 4, 0, },
178 CLK_SET_RATE_PARENT, 0xb8, 2, 0 },
180 CLK_SET_RATE_PARENT, 0xb8, 1, 0 },
182 CLK_SET_RATE_PARENT, 0xb8, 5, 0 },
184 CLK_SET_RATE_PARENT, 0xb8, 3, 0 },
186 CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
188 CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
191 CLK_SET_RATE_PARENT, 0xb0, 0, 0 },
193 CLK_SET_RATE_PARENT, 0xb0, 4, 0 },
195 CLK_SET_RATE_PARENT, 0xb0, 3, 0 },
197 CLK_SET_RATE_PARENT, 0xb0, 2, 0 },
199 CLK_SET_RATE_PARENT, 0xb0, 16, 0 },
201 CLK_SET_RATE_PARENT, 0xb0, 20, 0 },
203 CLK_SET_RATE_PARENT, 0xb0, 19, 0 },
205 CLK_SET_RATE_PARENT, 0xb0, 18, 0 },
294 CLK_SET_RATE_PARENT, 0x48, 4, 0, },
296 CLK_SET_RATE_PARENT, 0x48, 6, 0, },
298 CLK_SET_RATE_PARENT, 0x48, 10, 0, },