Lines Matching refs:CLK_SET_RATE_PARENT

298 					CLK_SET_RATE_PARENT, 0),
421 			DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
435 			DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
438 			DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
442 			DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
445 			DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
454 			DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
457 			DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
461 			DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
494 			SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
496 			SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
498 			SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
500 			SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
502 			SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
505 			SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
507 			SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
509 			SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
514 			SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
517 			SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
519 			SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
521 			SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
523 			SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
525 			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
527 			SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
530 			SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
533 			SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
535 			SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
537 			SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
539 			SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
541 			SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
544 			SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
546 			SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
550 			SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
552 			SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
554 			SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
588 					CLK_SET_RATE_PARENT, 0),