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/Linux-v6.1/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/power/xlnx-zynqmp-power.h>
17 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
20 compatible = "xlnx,zynqmp";
21 #address-cells = <2>;
22 #size-cells = <2>;
25 #address-cells = <1>;
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/Linux-v6.1/Documentation/devicetree/bindings/dma/xilinx/
Dxlnx,zynqmp-dpdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings
10 These bindings describe the DMA engine included in the Xilinx ZynqMP
11 DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
12 channels for a video stream, 1 channel for a graphics stream, and 2 channels
16 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 - $ref: "../dma-controller.yaml#"
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Dxlnx,zynqmp-dma-1.0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DMA Engine
10 The Xilinx ZynqMP DMA engine supports memory to memory transfers,
12 control and rate control support for slave/peripheral dma access.
15 - Michael Tretter <m.tretter@pengutronix.de>
18 - $ref: "../dma-controller.yaml#"
21 "#dma-cells":
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/Linux-v6.1/drivers/dma/xilinx/
Dzynqmp_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DMA driver for Xilinx ZynqMP DMA Engine
9 #include <linux/dma-mapping.h>
18 #include <linux/io-64-nonatomic-lo-hi.h>
67 /* Control 1 register bit field definitions */
140 #define ZYNQMP_DMA_DESC_SIZE(chan) (chan->desc_size)
148 * struct zynqmp_dma_desc_ll - Hw linked list descriptor
164 * struct zynqmp_dma_desc_sw - Per Transaction structure
165 * @src: Source address for simple mode dma
166 * @dst: Destination address for simple mode dma
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Dxilinx_dpdma.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP DPDMA Engine driver
5 * Copyright (C) 2015 - 2020 Xilinx, Inc.
15 #include <linux/dma/xilinx_dpdma.h>
28 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
31 #include "../virt-dma.h"
63 #define XILINX_DPDMA_EINTR_RD_AXI_ERR(n) BIT((n) + 1)
64 #define XILINX_DPDMA_EINTR_RD_AXI_ERR_MASK GENMASK(6, 1)
107 #define XILINX_DPDMA_CH_CNTL_PAUSE BIT(1)
142 * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor
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/Linux-v6.1/Documentation/devicetree/bindings/usb/
Ddwc3-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manish Narani <manish.narani@xilinx.com>
15 - enum:
16 - xlnx,zynqmp-dwc3
17 - xlnx,versal-dwc3
19 maxItems: 1
21 "#address-cells":
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/Linux-v6.1/Documentation/devicetree/bindings/display/xlnx/
Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
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/Linux-v6.1/drivers/gpu/drm/xlnx/
Dzynqmp_dpsub.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP DisplayPort Subsystem Driver
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 #include <linux/dma-mapping.h>
36 /* -----------------------------------------------------------------------------
45 unsigned int pitch = DIV_ROUND_UP(args->width * args->bpp, 8); in zynqmp_dpsub_dumb_create()
47 /* Enforce the alignment constraints of the DMA engine. */ in zynqmp_dpsub_dumb_create()
48 args->pitch = ALIGN(pitch, dpsub->dma_align); in zynqmp_dpsub_dumb_create()
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Dzynqmp_disp.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP Display Controller Driver
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
27 #include <linux/dma/xilinx_dpdma.h>
28 #include <linux/dma-mapping.h>
43 * --------
45 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video
48 * +------------------------------------------------------------+
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/Linux-v6.1/drivers/crypto/xilinx/
Dzynqmp-sha.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP SHA Driver.
12 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
25 ZYNQMP_SHA3_INIT = 1,
56 tfm_ctx->dev = drv_ctx->dev; in zynqmp_sha_init_tfm()
64 tfm_ctx->fbk_tfm = fallback_tfm; in zynqmp_sha_init_tfm()
65 hash->descsize += crypto_shash_descsize(tfm_ctx->fbk_tfm); in zynqmp_sha_init_tfm()
74 if (tfm_ctx->fbk_tfm) { in zynqmp_sha_exit_tfm()
75 crypto_free_shash(tfm_ctx->fbk_tfm); in zynqmp_sha_exit_tfm()
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Dzynqmp-aes-gcm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP AES Driver.
13 #include <linux/dma-mapping.h>
18 #include <linux/firmware/xlnx-zynqmp.h>
24 #define ZYNQMP_KEY_SRC_SEL_KEY_LEN 1U
25 #define ZYNQMP_AES_BLK_SIZE 1U
82 struct device *dev = tfm_ctx->dev; in zynqmp_aes_aead_cipher()
92 if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY) in zynqmp_aes_aead_cipher()
93 dma_size = req->cryptlen + ZYNQMP_AES_KEY_SIZE in zynqmp_aes_aead_cipher()
96 dma_size = req->cryptlen + GCM_AES_IV_SIZE; in zynqmp_aes_aead_cipher()
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/Linux-v6.1/drivers/dma/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # DMA engine configuration
7 bool "DMA Engine support"
10 DMA engines can do asynchronous data transfers without
14 DMA Device drivers supported by the configured arch, it may
18 bool "DMA Engine debugging"
22 say N here. This enables DMA engine core and driver debugging.
25 bool "DMA Engine verbose debugging"
30 the DMA engine core and drivers.
35 comment "DMA Devices"
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/Linux-v6.1/Documentation/devicetree/bindings/ata/
Dceva,ahci-1v84.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Piyush Mehta <piyush.mehta@xilinx.com>
14 special extensions to add functionality, is a high-performance dual-port
21 const: ceva,ahci-1v84
24 maxItems: 1
27 maxItems: 1
29 dma-coherent: true
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/Linux-v6.1/drivers/usb/dwc3/
Ddwc3-xilinx.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver
15 #include <linux/dma-mapping.h>
22 #include <linux/firmware/xlnx-zynqmp.h>
39 #define PIPE_CLK_DESELECT 1
62 reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()
69 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()
74 struct device *dev = priv_data->dev; in dwc3_xlnx_init_versal()
79 /* Assert and De-assert reset */ in dwc3_xlnx_init_versal()
90 dev_err_probe(dev, ret, "failed to De-assert Reset\n"); in dwc3_xlnx_init_versal()
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/Linux-v6.1/drivers/spi/
Dspi-zynqmp-gqspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
24 #include <linux/spi/spi-mem.h>
119 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
135 #define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */
143 * struct zynqmp_qspi - Defines qspi driver instance
155 * @dma_rx_bytes: Remaining bytes to receive by DMA mode
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
138 supports spi-mem interface.
208 this code to manage the per-word or per-transfer accesses to the
229 used by Xilinx Zynq and ZynqMP.
238 Flash over 1/2/4-bit wide bus. Enable this option if you have a
258 This enables dedicated general purpose SPI/Microwire1-compatible
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Dspi-cadence-quadspi.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
31 #include <linux/spi/spi-mem.h>
34 #define CQSPI_NAME "cadence-qspi"
39 #define CQSPI_DISABLE_DAC_MODE BIT(1)
155 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1
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/Linux-v6.1/drivers/net/ethernet/cadence/
Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
84 #define GEM_DMACFG 0x0010 /* DMA Configuration */
110 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
111 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
112 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
113 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
114 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
131 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
132 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
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Dmacb_main.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
41 #include <linux/firmware/xlnx-zynqmp.h>
58 * (bp)->rx_ring_size)
64 * (bp)->tx_ring_size)
67 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
78 …define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX…
80 * false amba_error in TX path from the DMA assuming there is not enough
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/Linux-v6.1/drivers/mtd/nand/raw/
Darasan-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
63 #define READ_READY BIT(1)
79 #define TCCS_TIME_100NS 1
114 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
124 * struct anfc_op - Defines how to execute an operation
126 * @addr1_reg: Memory address 1 register
150 * struct anand - Defines the NAND chip related information
153 * @rb: Ready-busy line
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/Linux-v6.1/
DMAINTAINERS9 -------------------------
11 1. Always *test* your changes, however small, on at least 4 or
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
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