1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
4 * (master mode only)
5 *
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/dmaengine.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_address.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/spi/spi.h>
22 #include <linux/spinlock.h>
23 #include <linux/workqueue.h>
24 #include <linux/spi/spi-mem.h>
25
26 /* Generic QSPI register offsets */
27 #define GQSPI_CONFIG_OFST 0x00000100
28 #define GQSPI_ISR_OFST 0x00000104
29 #define GQSPI_IDR_OFST 0x0000010C
30 #define GQSPI_IER_OFST 0x00000108
31 #define GQSPI_IMASK_OFST 0x00000110
32 #define GQSPI_EN_OFST 0x00000114
33 #define GQSPI_TXD_OFST 0x0000011C
34 #define GQSPI_RXD_OFST 0x00000120
35 #define GQSPI_TX_THRESHOLD_OFST 0x00000128
36 #define GQSPI_RX_THRESHOLD_OFST 0x0000012C
37 #define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138
38 #define GQSPI_GEN_FIFO_OFST 0x00000140
39 #define GQSPI_SEL_OFST 0x00000144
40 #define GQSPI_GF_THRESHOLD_OFST 0x00000150
41 #define GQSPI_FIFO_CTRL_OFST 0x0000014C
42 #define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C
43 #define GQSPI_QSPIDMA_DST_SIZE_OFST 0x00000804
44 #define GQSPI_QSPIDMA_DST_STS_OFST 0x00000808
45 #define GQSPI_QSPIDMA_DST_I_STS_OFST 0x00000814
46 #define GQSPI_QSPIDMA_DST_I_EN_OFST 0x00000818
47 #define GQSPI_QSPIDMA_DST_I_DIS_OFST 0x0000081C
48 #define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820
49 #define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800
50 #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
51
52 /* GQSPI register bit masks */
53 #define GQSPI_SEL_MASK 0x00000001
54 #define GQSPI_EN_MASK 0x00000001
55 #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020
56 #define GQSPI_ISR_WR_TO_CLR_MASK 0x00000002
57 #define GQSPI_IDR_ALL_MASK 0x00000FBE
58 #define GQSPI_CFG_MODE_EN_MASK 0xC0000000
59 #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK 0x20000000
60 #define GQSPI_CFG_ENDIAN_MASK 0x04000000
61 #define GQSPI_CFG_EN_POLL_TO_MASK 0x00100000
62 #define GQSPI_CFG_WP_HOLD_MASK 0x00080000
63 #define GQSPI_CFG_BAUD_RATE_DIV_MASK 0x00000038
64 #define GQSPI_CFG_CLK_PHA_MASK 0x00000004
65 #define GQSPI_CFG_CLK_POL_MASK 0x00000002
66 #define GQSPI_CFG_START_GEN_FIFO_MASK 0x10000000
67 #define GQSPI_GENFIFO_IMM_DATA_MASK 0x000000FF
68 #define GQSPI_GENFIFO_DATA_XFER 0x00000100
69 #define GQSPI_GENFIFO_EXP 0x00000200
70 #define GQSPI_GENFIFO_MODE_SPI 0x00000400
71 #define GQSPI_GENFIFO_MODE_DUALSPI 0x00000800
72 #define GQSPI_GENFIFO_MODE_QUADSPI 0x00000C00
73 #define GQSPI_GENFIFO_MODE_MASK 0x00000C00
74 #define GQSPI_GENFIFO_CS_LOWER 0x00001000
75 #define GQSPI_GENFIFO_CS_UPPER 0x00002000
76 #define GQSPI_GENFIFO_BUS_LOWER 0x00004000
77 #define GQSPI_GENFIFO_BUS_UPPER 0x00008000
78 #define GQSPI_GENFIFO_BUS_BOTH 0x0000C000
79 #define GQSPI_GENFIFO_BUS_MASK 0x0000C000
80 #define GQSPI_GENFIFO_TX 0x00010000
81 #define GQSPI_GENFIFO_RX 0x00020000
82 #define GQSPI_GENFIFO_STRIPE 0x00040000
83 #define GQSPI_GENFIFO_POLL 0x00080000
84 #define GQSPI_GENFIFO_EXP_START 0x00000100
85 #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004
86 #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002
87 #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001
88 #define GQSPI_ISR_RXEMPTY_MASK 0x00000800
89 #define GQSPI_ISR_GENFIFOFULL_MASK 0x00000400
90 #define GQSPI_ISR_GENFIFONOT_FULL_MASK 0x00000200
91 #define GQSPI_ISR_TXEMPTY_MASK 0x00000100
92 #define GQSPI_ISR_GENFIFOEMPTY_MASK 0x00000080
93 #define GQSPI_ISR_RXFULL_MASK 0x00000020
94 #define GQSPI_ISR_RXNEMPTY_MASK 0x00000010
95 #define GQSPI_ISR_TXFULL_MASK 0x00000008
96 #define GQSPI_ISR_TXNOT_FULL_MASK 0x00000004
97 #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK 0x00000002
98 #define GQSPI_IER_TXNOT_FULL_MASK 0x00000004
99 #define GQSPI_IER_RXEMPTY_MASK 0x00000800
100 #define GQSPI_IER_POLL_TIME_EXPIRE_MASK 0x00000002
101 #define GQSPI_IER_RXNEMPTY_MASK 0x00000010
102 #define GQSPI_IER_GENFIFOEMPTY_MASK 0x00000080
103 #define GQSPI_IER_TXEMPTY_MASK 0x00000100
104 #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK 0x000000FE
105 #define GQSPI_QSPIDMA_DST_STS_WTC 0x0000E000
106 #define GQSPI_CFG_MODE_EN_DMA_MASK 0x80000000
107 #define GQSPI_ISR_IDR_MASK 0x00000994
108 #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK 0x00000002
109 #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK 0x00000002
110 #define GQSPI_IRQ_MASK 0x00000980
111
112 #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT 3
113 #define GQSPI_GENFIFO_CS_SETUP 0x4
114 #define GQSPI_GENFIFO_CS_HOLD 0x3
115 #define GQSPI_TXD_DEPTH 64
116 #define GQSPI_RX_FIFO_THRESHOLD 32
117 #define GQSPI_RX_FIFO_FILL (GQSPI_RX_FIFO_THRESHOLD * 4)
118 #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL 32
119 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
120 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
121 #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL 0X10
122 #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00
123 #define GQSPI_SELECT_FLASH_CS_LOWER 0x1
124 #define GQSPI_SELECT_FLASH_CS_UPPER 0x2
125 #define GQSPI_SELECT_FLASH_CS_BOTH 0x3
126 #define GQSPI_SELECT_FLASH_BUS_LOWER 0x1
127 #define GQSPI_SELECT_FLASH_BUS_UPPER 0x2
128 #define GQSPI_SELECT_FLASH_BUS_BOTH 0x3
129 #define GQSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
130 #define GQSPI_BAUD_DIV_SHIFT 2 /* Baud rate divisor shift */
131 #define GQSPI_SELECT_MODE_SPI 0x1
132 #define GQSPI_SELECT_MODE_DUALSPI 0x2
133 #define GQSPI_SELECT_MODE_QUADSPI 0x4
134 #define GQSPI_DMA_UNALIGN 0x3
135 #define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */
136
137 #define GQSPI_MAX_NUM_CS 2 /* Maximum number of chip selects */
138
139 #define SPI_AUTOSUSPEND_TIMEOUT 3000
140 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
141
142 /**
143 * struct zynqmp_qspi - Defines qspi driver instance
144 * @regs: Virtual address of the QSPI controller registers
145 * @refclk: Pointer to the peripheral clock
146 * @pclk: Pointer to the APB clock
147 * @irq: IRQ number
148 * @dev: Pointer to struct device
149 * @txbuf: Pointer to the TX buffer
150 * @rxbuf: Pointer to the RX buffer
151 * @bytes_to_transfer: Number of bytes left to transfer
152 * @bytes_to_receive: Number of bytes left to receive
153 * @genfifocs: Used for chip select
154 * @genfifobus: Used to select the upper or lower bus
155 * @dma_rx_bytes: Remaining bytes to receive by DMA mode
156 * @dma_addr: DMA address after mapping the kernel buffer
157 * @genfifoentry: Used for storing the genfifoentry instruction.
158 * @mode: Defines the mode in which QSPI is operating
159 * @data_completion: completion structure
160 */
161 struct zynqmp_qspi {
162 struct spi_controller *ctlr;
163 void __iomem *regs;
164 struct clk *refclk;
165 struct clk *pclk;
166 int irq;
167 struct device *dev;
168 const void *txbuf;
169 void *rxbuf;
170 int bytes_to_transfer;
171 int bytes_to_receive;
172 u32 genfifocs;
173 u32 genfifobus;
174 u32 dma_rx_bytes;
175 dma_addr_t dma_addr;
176 u32 genfifoentry;
177 enum mode_type mode;
178 struct completion data_completion;
179 struct mutex op_lock;
180 };
181
182 /**
183 * zynqmp_gqspi_read - For GQSPI controller read operation
184 * @xqspi: Pointer to the zynqmp_qspi structure
185 * @offset: Offset from where to read
186 * Return: Value at the offset
187 */
zynqmp_gqspi_read(struct zynqmp_qspi * xqspi,u32 offset)188 static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
189 {
190 return readl_relaxed(xqspi->regs + offset);
191 }
192
193 /**
194 * zynqmp_gqspi_write - For GQSPI controller write operation
195 * @xqspi: Pointer to the zynqmp_qspi structure
196 * @offset: Offset where to write
197 * @val: Value to be written
198 */
zynqmp_gqspi_write(struct zynqmp_qspi * xqspi,u32 offset,u32 val)199 static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
200 u32 val)
201 {
202 writel_relaxed(val, (xqspi->regs + offset));
203 }
204
205 /**
206 * zynqmp_gqspi_selectslave - For selection of slave device
207 * @instanceptr: Pointer to the zynqmp_qspi structure
208 * @slavecs: For chip select
209 * @slavebus: To check which bus is selected- upper or lower
210 */
zynqmp_gqspi_selectslave(struct zynqmp_qspi * instanceptr,u8 slavecs,u8 slavebus)211 static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
212 u8 slavecs, u8 slavebus)
213 {
214 /*
215 * Bus and CS lines selected here will be updated in the instance and
216 * used for subsequent GENFIFO entries during transfer.
217 */
218
219 /* Choose slave select line */
220 switch (slavecs) {
221 case GQSPI_SELECT_FLASH_CS_BOTH:
222 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
223 GQSPI_GENFIFO_CS_UPPER;
224 break;
225 case GQSPI_SELECT_FLASH_CS_UPPER:
226 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
227 break;
228 case GQSPI_SELECT_FLASH_CS_LOWER:
229 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
230 break;
231 default:
232 dev_warn(instanceptr->dev, "Invalid slave select\n");
233 }
234
235 /* Choose the bus */
236 switch (slavebus) {
237 case GQSPI_SELECT_FLASH_BUS_BOTH:
238 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
239 GQSPI_GENFIFO_BUS_UPPER;
240 break;
241 case GQSPI_SELECT_FLASH_BUS_UPPER:
242 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
243 break;
244 case GQSPI_SELECT_FLASH_BUS_LOWER:
245 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
246 break;
247 default:
248 dev_warn(instanceptr->dev, "Invalid slave bus\n");
249 }
250 }
251
252 /**
253 * zynqmp_qspi_init_hw - Initialize the hardware
254 * @xqspi: Pointer to the zynqmp_qspi structure
255 *
256 * The default settings of the QSPI controller's configurable parameters on
257 * reset are
258 * - Master mode
259 * - TX threshold set to 1
260 * - RX threshold set to 1
261 * - Flash memory interface mode enabled
262 * This function performs the following actions
263 * - Disable and clear all the interrupts
264 * - Enable manual slave select
265 * - Enable manual start
266 * - Deselect all the chip select lines
267 * - Set the little endian mode of TX FIFO and
268 * - Enable the QSPI controller
269 */
zynqmp_qspi_init_hw(struct zynqmp_qspi * xqspi)270 static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
271 {
272 u32 config_reg;
273
274 /* Select the GQSPI mode */
275 zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
276 /* Clear and disable interrupts */
277 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
278 zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
279 GQSPI_ISR_WR_TO_CLR_MASK);
280 /* Clear the DMA STS */
281 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
282 zynqmp_gqspi_read(xqspi,
283 GQSPI_QSPIDMA_DST_I_STS_OFST));
284 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
285 zynqmp_gqspi_read(xqspi,
286 GQSPI_QSPIDMA_DST_STS_OFST) |
287 GQSPI_QSPIDMA_DST_STS_WTC);
288 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
289 zynqmp_gqspi_write(xqspi,
290 GQSPI_QSPIDMA_DST_I_DIS_OFST,
291 GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
292 /* Disable the GQSPI */
293 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
294 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
295 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
296 /* Manual start */
297 config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
298 /* Little endian by default */
299 config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
300 /* Disable poll time out */
301 config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
302 /* Set hold bit */
303 config_reg |= GQSPI_CFG_WP_HOLD_MASK;
304 /* Clear pre-scalar by default */
305 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
306 /* CPHA 0 */
307 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
308 /* CPOL 0 */
309 config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
310 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
311
312 /* Clear the TX and RX FIFO */
313 zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
314 GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
315 GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
316 GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
317 /* Set by default to allow for high frequencies */
318 zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
319 zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
320 GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
321 /* Reset thresholds */
322 zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
323 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
324 zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
325 GQSPI_RX_FIFO_THRESHOLD);
326 zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
327 GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
328 zynqmp_gqspi_selectslave(xqspi,
329 GQSPI_SELECT_FLASH_CS_LOWER,
330 GQSPI_SELECT_FLASH_BUS_LOWER);
331 /* Initialize DMA */
332 zynqmp_gqspi_write(xqspi,
333 GQSPI_QSPIDMA_DST_CTRL_OFST,
334 GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
335
336 /* Enable the GQSPI */
337 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
338 }
339
340 /**
341 * zynqmp_qspi_copy_read_data - Copy data to RX buffer
342 * @xqspi: Pointer to the zynqmp_qspi structure
343 * @data: The variable where data is stored
344 * @size: Number of bytes to be copied from data to RX buffer
345 */
zynqmp_qspi_copy_read_data(struct zynqmp_qspi * xqspi,ulong data,u8 size)346 static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
347 ulong data, u8 size)
348 {
349 memcpy(xqspi->rxbuf, &data, size);
350 xqspi->rxbuf += size;
351 xqspi->bytes_to_receive -= size;
352 }
353
354 /**
355 * zynqmp_qspi_chipselect - Select or deselect the chip select line
356 * @qspi: Pointer to the spi_device structure
357 * @is_high: Select(0) or deselect (1) the chip select line
358 */
zynqmp_qspi_chipselect(struct spi_device * qspi,bool is_high)359 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
360 {
361 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
362 ulong timeout;
363 u32 genfifoentry = 0, statusreg;
364
365 genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
366
367 if (!is_high) {
368 if (!qspi->chip_select) {
369 xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
370 xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
371 } else {
372 xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
373 xqspi->genfifocs = GQSPI_GENFIFO_CS_UPPER;
374 }
375 genfifoentry |= xqspi->genfifobus;
376 genfifoentry |= xqspi->genfifocs;
377 genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
378 } else {
379 genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
380 }
381
382 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
383
384 /* Manually start the generic FIFO command */
385 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
386 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
387 GQSPI_CFG_START_GEN_FIFO_MASK);
388
389 timeout = jiffies + msecs_to_jiffies(1000);
390
391 /* Wait until the generic FIFO command is empty */
392 do {
393 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
394
395 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
396 (statusreg & GQSPI_ISR_TXEMPTY_MASK))
397 break;
398 cpu_relax();
399 } while (!time_after_eq(jiffies, timeout));
400
401 if (time_after_eq(jiffies, timeout))
402 dev_err(xqspi->dev, "Chip select timed out\n");
403 }
404
405 /**
406 * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.
407 * @xqspi: xqspi is a pointer to the GQSPI instance
408 * @spimode: spimode - SPI or DUAL or QUAD.
409 * Return: Mask to set desired SPI mode in GENFIFO entry.
410 */
zynqmp_qspi_selectspimode(struct zynqmp_qspi * xqspi,u8 spimode)411 static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
412 u8 spimode)
413 {
414 u32 mask = 0;
415
416 switch (spimode) {
417 case GQSPI_SELECT_MODE_DUALSPI:
418 mask = GQSPI_GENFIFO_MODE_DUALSPI;
419 break;
420 case GQSPI_SELECT_MODE_QUADSPI:
421 mask = GQSPI_GENFIFO_MODE_QUADSPI;
422 break;
423 case GQSPI_SELECT_MODE_SPI:
424 mask = GQSPI_GENFIFO_MODE_SPI;
425 break;
426 default:
427 dev_warn(xqspi->dev, "Invalid SPI mode\n");
428 }
429
430 return mask;
431 }
432
433 /**
434 * zynqmp_qspi_config_op - Configure QSPI controller for specified
435 * transfer
436 * @xqspi: Pointer to the zynqmp_qspi structure
437 * @qspi: Pointer to the spi_device structure
438 *
439 * Sets the operational mode of QSPI controller for the next QSPI transfer and
440 * sets the requested clock frequency.
441 *
442 * Return: Always 0
443 *
444 * Note:
445 * If the requested frequency is not an exact match with what can be
446 * obtained using the pre-scalar value, the driver sets the clock
447 * frequency which is lower than the requested frequency (maximum lower)
448 * for the transfer.
449 *
450 * If the requested frequency is higher or lower than that is supported
451 * by the QSPI controller the driver will set the highest or lowest
452 * frequency supported by controller.
453 */
zynqmp_qspi_config_op(struct zynqmp_qspi * xqspi,struct spi_device * qspi)454 static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,
455 struct spi_device *qspi)
456 {
457 ulong clk_rate;
458 u32 config_reg, baud_rate_val = 0;
459
460 /* Set the clock frequency */
461 /* If req_hz == 0, default to lowest speed */
462 clk_rate = clk_get_rate(xqspi->refclk);
463
464 while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
465 (clk_rate /
466 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > qspi->max_speed_hz)
467 baud_rate_val++;
468
469 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
470
471 /* Set the QSPI clock phase and clock polarity */
472 config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
473
474 if (qspi->mode & SPI_CPHA)
475 config_reg |= GQSPI_CFG_CLK_PHA_MASK;
476 if (qspi->mode & SPI_CPOL)
477 config_reg |= GQSPI_CFG_CLK_POL_MASK;
478
479 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
480 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
481 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
482 return 0;
483 }
484
485 /**
486 * zynqmp_qspi_setup_op - Configure the QSPI controller
487 * @qspi: Pointer to the spi_device structure
488 *
489 * Sets the operational mode of QSPI controller for the next QSPI transfer,
490 * baud rate and divisor value to setup the requested qspi clock.
491 *
492 * Return: 0 on success; error value otherwise.
493 */
zynqmp_qspi_setup_op(struct spi_device * qspi)494 static int zynqmp_qspi_setup_op(struct spi_device *qspi)
495 {
496 struct spi_controller *ctlr = qspi->master;
497 struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
498
499 if (ctlr->busy)
500 return -EBUSY;
501
502 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
503
504 return 0;
505 }
506
507 /**
508 * zynqmp_qspi_filltxfifo - Fills the TX FIFO as long as there is room in
509 * the FIFO or the bytes required to be
510 * transmitted.
511 * @xqspi: Pointer to the zynqmp_qspi structure
512 * @size: Number of bytes to be copied from TX buffer to TX FIFO
513 */
zynqmp_qspi_filltxfifo(struct zynqmp_qspi * xqspi,int size)514 static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
515 {
516 u32 count = 0, intermediate;
517
518 while ((xqspi->bytes_to_transfer > 0) && (count < size) && (xqspi->txbuf)) {
519 if (xqspi->bytes_to_transfer >= 4) {
520 memcpy(&intermediate, xqspi->txbuf, 4);
521 xqspi->txbuf += 4;
522 xqspi->bytes_to_transfer -= 4;
523 count += 4;
524 } else {
525 memcpy(&intermediate, xqspi->txbuf,
526 xqspi->bytes_to_transfer);
527 xqspi->txbuf += xqspi->bytes_to_transfer;
528 xqspi->bytes_to_transfer = 0;
529 count += xqspi->bytes_to_transfer;
530 }
531 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
532 }
533 }
534
535 /**
536 * zynqmp_qspi_readrxfifo - Fills the RX FIFO as long as there is room in
537 * the FIFO.
538 * @xqspi: Pointer to the zynqmp_qspi structure
539 * @size: Number of bytes to be copied from RX buffer to RX FIFO
540 */
zynqmp_qspi_readrxfifo(struct zynqmp_qspi * xqspi,u32 size)541 static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
542 {
543 ulong data;
544 int count = 0;
545
546 while ((count < size) && (xqspi->bytes_to_receive > 0)) {
547 if (xqspi->bytes_to_receive >= 4) {
548 (*(u32 *)xqspi->rxbuf) =
549 zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
550 xqspi->rxbuf += 4;
551 xqspi->bytes_to_receive -= 4;
552 count += 4;
553 } else {
554 data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
555 count += xqspi->bytes_to_receive;
556 zynqmp_qspi_copy_read_data(xqspi, data,
557 xqspi->bytes_to_receive);
558 xqspi->bytes_to_receive = 0;
559 }
560 }
561 }
562
563 /**
564 * zynqmp_qspi_fillgenfifo - Fills the GENFIFO.
565 * @xqspi: Pointer to the zynqmp_qspi structure
566 * @nbits: Transfer/Receive buswidth.
567 * @genfifoentry: Variable in which GENFIFO mask is saved
568 */
zynqmp_qspi_fillgenfifo(struct zynqmp_qspi * xqspi,u8 nbits,u32 genfifoentry)569 static void zynqmp_qspi_fillgenfifo(struct zynqmp_qspi *xqspi, u8 nbits,
570 u32 genfifoentry)
571 {
572 u32 transfer_len = 0;
573
574 if (xqspi->txbuf) {
575 genfifoentry &= ~GQSPI_GENFIFO_RX;
576 genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
577 genfifoentry |= GQSPI_GENFIFO_TX;
578 transfer_len = xqspi->bytes_to_transfer;
579 } else if (xqspi->rxbuf) {
580 genfifoentry &= ~GQSPI_GENFIFO_TX;
581 genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
582 genfifoentry |= GQSPI_GENFIFO_RX;
583 if (xqspi->mode == GQSPI_MODE_DMA)
584 transfer_len = xqspi->dma_rx_bytes;
585 else
586 transfer_len = xqspi->bytes_to_receive;
587 } else {
588 /* Sending dummy circles here */
589 genfifoentry &= ~(GQSPI_GENFIFO_TX | GQSPI_GENFIFO_RX);
590 genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
591 transfer_len = xqspi->bytes_to_transfer;
592 }
593 genfifoentry |= zynqmp_qspi_selectspimode(xqspi, nbits);
594 xqspi->genfifoentry = genfifoentry;
595
596 if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
597 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
598 genfifoentry |= transfer_len;
599 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
600 } else {
601 int tempcount = transfer_len;
602 u32 exponent = 8; /* 2^8 = 256 */
603 u8 imm_data = tempcount & 0xFF;
604
605 tempcount &= ~(tempcount & 0xFF);
606 /* Immediate entry */
607 if (tempcount != 0) {
608 /* Exponent entries */
609 genfifoentry |= GQSPI_GENFIFO_EXP;
610 while (tempcount != 0) {
611 if (tempcount & GQSPI_GENFIFO_EXP_START) {
612 genfifoentry &=
613 ~GQSPI_GENFIFO_IMM_DATA_MASK;
614 genfifoentry |= exponent;
615 zynqmp_gqspi_write(xqspi,
616 GQSPI_GEN_FIFO_OFST,
617 genfifoentry);
618 }
619 tempcount = tempcount >> 1;
620 exponent++;
621 }
622 }
623 if (imm_data != 0) {
624 genfifoentry &= ~GQSPI_GENFIFO_EXP;
625 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
626 genfifoentry |= (u8)(imm_data & 0xFF);
627 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
628 genfifoentry);
629 }
630 }
631 if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf) {
632 /* Dummy generic FIFO entry */
633 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
634 }
635 }
636
637 /**
638 * zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI
639 * controller
640 * @xqspi: zynqmp_qspi instance pointer
641 *
642 * This function handles DMA interrupt only.
643 */
zynqmp_process_dma_irq(struct zynqmp_qspi * xqspi)644 static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
645 {
646 u32 config_reg, genfifoentry;
647
648 dma_unmap_single(xqspi->dev, xqspi->dma_addr,
649 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
650 xqspi->rxbuf += xqspi->dma_rx_bytes;
651 xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
652 xqspi->dma_rx_bytes = 0;
653
654 /* Disabling the DMA interrupts */
655 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
656 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
657
658 if (xqspi->bytes_to_receive > 0) {
659 /* Switch to IO mode,for remaining bytes to receive */
660 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
661 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
662 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
663
664 /* Initiate the transfer of remaining bytes */
665 genfifoentry = xqspi->genfifoentry;
666 genfifoentry |= xqspi->bytes_to_receive;
667 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
668
669 /* Dummy generic FIFO entry */
670 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
671
672 /* Manual start */
673 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
674 (zynqmp_gqspi_read(xqspi,
675 GQSPI_CONFIG_OFST) |
676 GQSPI_CFG_START_GEN_FIFO_MASK));
677
678 /* Enable the RX interrupts for IO mode */
679 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
680 GQSPI_IER_GENFIFOEMPTY_MASK |
681 GQSPI_IER_RXNEMPTY_MASK |
682 GQSPI_IER_RXEMPTY_MASK);
683 }
684 }
685
686 /**
687 * zynqmp_qspi_irq - Interrupt service routine of the QSPI controller
688 * @irq: IRQ number
689 * @dev_id: Pointer to the xqspi structure
690 *
691 * This function handles TX empty only.
692 * On TX empty interrupt this function reads the received data from RX FIFO
693 * and fills the TX FIFO if there is any data remaining to be transferred.
694 *
695 * Return: IRQ_HANDLED when interrupt is handled
696 * IRQ_NONE otherwise.
697 */
zynqmp_qspi_irq(int irq,void * dev_id)698 static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
699 {
700 struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_id;
701 irqreturn_t ret = IRQ_NONE;
702 u32 status, mask, dma_status = 0;
703
704 status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
705 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
706 mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
707
708 /* Read and clear DMA status */
709 if (xqspi->mode == GQSPI_MODE_DMA) {
710 dma_status =
711 zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
712 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
713 dma_status);
714 }
715
716 if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
717 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
718 ret = IRQ_HANDLED;
719 }
720
721 if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
722 zynqmp_process_dma_irq(xqspi);
723 ret = IRQ_HANDLED;
724 } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
725 (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
726 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
727 ret = IRQ_HANDLED;
728 }
729
730 if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 &&
731 ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
732 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
733 complete(&xqspi->data_completion);
734 ret = IRQ_HANDLED;
735 }
736 return ret;
737 }
738
739 /**
740 * zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
741 * @xqspi: xqspi is a pointer to the GQSPI instance.
742 */
zynqmp_qspi_setuprxdma(struct zynqmp_qspi * xqspi)743 static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
744 {
745 u32 rx_bytes, rx_rem, config_reg;
746 dma_addr_t addr;
747 u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf;
748
749 if (xqspi->bytes_to_receive < 8 ||
750 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
751 /* Setting to IO mode */
752 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
753 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
754 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
755 xqspi->mode = GQSPI_MODE_IO;
756 xqspi->dma_rx_bytes = 0;
757 return 0;
758 }
759
760 rx_rem = xqspi->bytes_to_receive % 4;
761 rx_bytes = (xqspi->bytes_to_receive - rx_rem);
762
763 addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
764 rx_bytes, DMA_FROM_DEVICE);
765 if (dma_mapping_error(xqspi->dev, addr)) {
766 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
767 return -ENOMEM;
768 }
769
770 xqspi->dma_rx_bytes = rx_bytes;
771 xqspi->dma_addr = addr;
772 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
773 (u32)(addr & 0xffffffff));
774 addr = ((addr >> 16) >> 16);
775 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
776 ((u32)addr) & 0xfff);
777
778 /* Enabling the DMA mode */
779 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
780 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
781 config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
782 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
783
784 /* Switch to DMA mode */
785 xqspi->mode = GQSPI_MODE_DMA;
786
787 /* Write the number of bytes to transfer */
788 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
789
790 return 0;
791 }
792
793 /**
794 * zynqmp_qspi_write_op - This function sets up the GENFIFO entries,
795 * TX FIFO, and fills the TX FIFO with as many
796 * bytes as possible.
797 * @xqspi: Pointer to the GQSPI instance.
798 * @tx_nbits: Transfer buswidth.
799 * @genfifoentry: Variable in which GENFIFO mask is returned
800 * to calling function
801 */
zynqmp_qspi_write_op(struct zynqmp_qspi * xqspi,u8 tx_nbits,u32 genfifoentry)802 static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits,
803 u32 genfifoentry)
804 {
805 u32 config_reg;
806
807 zynqmp_qspi_fillgenfifo(xqspi, tx_nbits, genfifoentry);
808 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
809 if (xqspi->mode == GQSPI_MODE_DMA) {
810 config_reg = zynqmp_gqspi_read(xqspi,
811 GQSPI_CONFIG_OFST);
812 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
813 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
814 config_reg);
815 xqspi->mode = GQSPI_MODE_IO;
816 }
817 }
818
819 /**
820 * zynqmp_qspi_read_op - This function sets up the GENFIFO entries and
821 * RX DMA operation.
822 * @xqspi: xqspi is a pointer to the GQSPI instance.
823 * @rx_nbits: Receive buswidth.
824 * @genfifoentry: genfifoentry is pointer to the variable in which
825 * GENFIFO mask is returned to calling function
826 */
zynqmp_qspi_read_op(struct zynqmp_qspi * xqspi,u8 rx_nbits,u32 genfifoentry)827 static int zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits,
828 u32 genfifoentry)
829 {
830 int ret;
831
832 ret = zynqmp_qspi_setuprxdma(xqspi);
833 if (ret)
834 return ret;
835 zynqmp_qspi_fillgenfifo(xqspi, rx_nbits, genfifoentry);
836
837 return 0;
838 }
839
840 /**
841 * zynqmp_qspi_suspend - Suspend method for the QSPI driver
842 * @dev: Address of the platform_device structure
843 *
844 * This function stops the QSPI driver queue and disables the QSPI controller
845 *
846 * Return: Always 0
847 */
zynqmp_qspi_suspend(struct device * dev)848 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
849 {
850 struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
851 struct spi_controller *ctlr = xqspi->ctlr;
852 int ret;
853
854 ret = spi_controller_suspend(ctlr);
855 if (ret)
856 return ret;
857
858 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
859
860 return 0;
861 }
862
863 /**
864 * zynqmp_qspi_resume - Resume method for the QSPI driver
865 * @dev: Address of the platform_device structure
866 *
867 * The function starts the QSPI driver queue and initializes the QSPI
868 * controller
869 *
870 * Return: 0 on success; error value otherwise
871 */
zynqmp_qspi_resume(struct device * dev)872 static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
873 {
874 struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
875 struct spi_controller *ctlr = xqspi->ctlr;
876
877 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
878
879 spi_controller_resume(ctlr);
880
881 return 0;
882 }
883
884 /**
885 * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
886 * @dev: Address of the platform_device structure
887 *
888 * This function disables the clocks
889 *
890 * Return: Always 0
891 */
zynqmp_runtime_suspend(struct device * dev)892 static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
893 {
894 struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
895
896 clk_disable_unprepare(xqspi->refclk);
897 clk_disable_unprepare(xqspi->pclk);
898
899 return 0;
900 }
901
902 /**
903 * zynqmp_runtime_resume - Runtime resume method for the SPI driver
904 * @dev: Address of the platform_device structure
905 *
906 * This function enables the clocks
907 *
908 * Return: 0 on success and error value on error
909 */
zynqmp_runtime_resume(struct device * dev)910 static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
911 {
912 struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
913 int ret;
914
915 ret = clk_prepare_enable(xqspi->pclk);
916 if (ret) {
917 dev_err(dev, "Cannot enable APB clock.\n");
918 return ret;
919 }
920
921 ret = clk_prepare_enable(xqspi->refclk);
922 if (ret) {
923 dev_err(dev, "Cannot enable device clock.\n");
924 clk_disable_unprepare(xqspi->pclk);
925 return ret;
926 }
927
928 return 0;
929 }
930
931 /**
932 * zynqmp_qspi_exec_op() - Initiates the QSPI transfer
933 * @mem: The SPI memory
934 * @op: The memory operation to execute
935 *
936 * Executes a memory operation.
937 *
938 * This function first selects the chip and starts the memory operation.
939 *
940 * Return: 0 in case of success, a negative error code otherwise.
941 */
zynqmp_qspi_exec_op(struct spi_mem * mem,const struct spi_mem_op * op)942 static int zynqmp_qspi_exec_op(struct spi_mem *mem,
943 const struct spi_mem_op *op)
944 {
945 struct zynqmp_qspi *xqspi = spi_controller_get_devdata
946 (mem->spi->master);
947 int err = 0, i;
948 u32 genfifoentry = 0;
949 u16 opcode = op->cmd.opcode;
950 u64 opaddr;
951
952 dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
953 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
954 op->dummy.buswidth, op->data.buswidth);
955
956 mutex_lock(&xqspi->op_lock);
957 zynqmp_qspi_config_op(xqspi, mem->spi);
958 zynqmp_qspi_chipselect(mem->spi, false);
959 genfifoentry |= xqspi->genfifocs;
960 genfifoentry |= xqspi->genfifobus;
961
962 if (op->cmd.opcode) {
963 reinit_completion(&xqspi->data_completion);
964 xqspi->txbuf = &opcode;
965 xqspi->rxbuf = NULL;
966 xqspi->bytes_to_transfer = op->cmd.nbytes;
967 xqspi->bytes_to_receive = 0;
968 zynqmp_qspi_write_op(xqspi, op->cmd.buswidth, genfifoentry);
969 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
970 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
971 GQSPI_CFG_START_GEN_FIFO_MASK);
972 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
973 GQSPI_IER_GENFIFOEMPTY_MASK |
974 GQSPI_IER_TXNOT_FULL_MASK);
975 if (!wait_for_completion_timeout
976 (&xqspi->data_completion, msecs_to_jiffies(1000))) {
977 err = -ETIMEDOUT;
978 goto return_err;
979 }
980 }
981
982 if (op->addr.nbytes) {
983 xqspi->txbuf = &opaddr;
984 for (i = 0; i < op->addr.nbytes; i++) {
985 *(((u8 *)xqspi->txbuf) + i) = op->addr.val >>
986 (8 * (op->addr.nbytes - i - 1));
987 }
988
989 reinit_completion(&xqspi->data_completion);
990 xqspi->rxbuf = NULL;
991 xqspi->bytes_to_transfer = op->addr.nbytes;
992 xqspi->bytes_to_receive = 0;
993 zynqmp_qspi_write_op(xqspi, op->addr.buswidth, genfifoentry);
994 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
995 zynqmp_gqspi_read(xqspi,
996 GQSPI_CONFIG_OFST) |
997 GQSPI_CFG_START_GEN_FIFO_MASK);
998 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
999 GQSPI_IER_TXEMPTY_MASK |
1000 GQSPI_IER_GENFIFOEMPTY_MASK |
1001 GQSPI_IER_TXNOT_FULL_MASK);
1002 if (!wait_for_completion_timeout
1003 (&xqspi->data_completion, msecs_to_jiffies(1000))) {
1004 err = -ETIMEDOUT;
1005 goto return_err;
1006 }
1007 }
1008
1009 if (op->dummy.nbytes) {
1010 xqspi->txbuf = NULL;
1011 xqspi->rxbuf = NULL;
1012 /*
1013 * xqspi->bytes_to_transfer here represents the dummy circles
1014 * which need to be sent.
1015 */
1016 xqspi->bytes_to_transfer = op->dummy.nbytes * 8 / op->dummy.buswidth;
1017 xqspi->bytes_to_receive = 0;
1018 /*
1019 * Using op->data.buswidth instead of op->dummy.buswidth here because
1020 * we need to use it to configure the correct SPI mode.
1021 */
1022 zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1023 genfifoentry);
1024 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1025 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
1026 GQSPI_CFG_START_GEN_FIFO_MASK);
1027 }
1028
1029 if (op->data.nbytes) {
1030 reinit_completion(&xqspi->data_completion);
1031 if (op->data.dir == SPI_MEM_DATA_OUT) {
1032 xqspi->txbuf = (u8 *)op->data.buf.out;
1033 xqspi->rxbuf = NULL;
1034 xqspi->bytes_to_transfer = op->data.nbytes;
1035 xqspi->bytes_to_receive = 0;
1036 zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1037 genfifoentry);
1038 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1039 zynqmp_gqspi_read
1040 (xqspi, GQSPI_CONFIG_OFST) |
1041 GQSPI_CFG_START_GEN_FIFO_MASK);
1042 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1043 GQSPI_IER_TXEMPTY_MASK |
1044 GQSPI_IER_GENFIFOEMPTY_MASK |
1045 GQSPI_IER_TXNOT_FULL_MASK);
1046 } else {
1047 xqspi->txbuf = NULL;
1048 xqspi->rxbuf = (u8 *)op->data.buf.in;
1049 xqspi->bytes_to_receive = op->data.nbytes;
1050 xqspi->bytes_to_transfer = 0;
1051 err = zynqmp_qspi_read_op(xqspi, op->data.buswidth,
1052 genfifoentry);
1053 if (err)
1054 goto return_err;
1055
1056 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1057 zynqmp_gqspi_read
1058 (xqspi, GQSPI_CONFIG_OFST) |
1059 GQSPI_CFG_START_GEN_FIFO_MASK);
1060 if (xqspi->mode == GQSPI_MODE_DMA) {
1061 zynqmp_gqspi_write
1062 (xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST,
1063 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
1064 } else {
1065 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1066 GQSPI_IER_GENFIFOEMPTY_MASK |
1067 GQSPI_IER_RXNEMPTY_MASK |
1068 GQSPI_IER_RXEMPTY_MASK);
1069 }
1070 }
1071 if (!wait_for_completion_timeout
1072 (&xqspi->data_completion, msecs_to_jiffies(1000)))
1073 err = -ETIMEDOUT;
1074 }
1075
1076 return_err:
1077
1078 zynqmp_qspi_chipselect(mem->spi, true);
1079 mutex_unlock(&xqspi->op_lock);
1080
1081 return err;
1082 }
1083
1084 static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
1085 SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
1086 zynqmp_runtime_resume, NULL)
1087 SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
1088 };
1089
1090 static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
1091 .exec_op = zynqmp_qspi_exec_op,
1092 };
1093
1094 /**
1095 * zynqmp_qspi_probe - Probe method for the QSPI driver
1096 * @pdev: Pointer to the platform_device structure
1097 *
1098 * This function initializes the driver data structures and the hardware.
1099 *
1100 * Return: 0 on success; error value otherwise
1101 */
zynqmp_qspi_probe(struct platform_device * pdev)1102 static int zynqmp_qspi_probe(struct platform_device *pdev)
1103 {
1104 int ret = 0;
1105 struct spi_controller *ctlr;
1106 struct zynqmp_qspi *xqspi;
1107 struct device *dev = &pdev->dev;
1108 struct device_node *np = dev->of_node;
1109 u32 num_cs;
1110
1111 ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1112 if (!ctlr)
1113 return -ENOMEM;
1114
1115 xqspi = spi_controller_get_devdata(ctlr);
1116 xqspi->dev = dev;
1117 xqspi->ctlr = ctlr;
1118 platform_set_drvdata(pdev, xqspi);
1119
1120 xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
1121 if (IS_ERR(xqspi->regs)) {
1122 ret = PTR_ERR(xqspi->regs);
1123 goto remove_master;
1124 }
1125
1126 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1127 if (IS_ERR(xqspi->pclk)) {
1128 dev_err(dev, "pclk clock not found.\n");
1129 ret = PTR_ERR(xqspi->pclk);
1130 goto remove_master;
1131 }
1132
1133 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1134 if (IS_ERR(xqspi->refclk)) {
1135 dev_err(dev, "ref_clk clock not found.\n");
1136 ret = PTR_ERR(xqspi->refclk);
1137 goto remove_master;
1138 }
1139
1140 ret = clk_prepare_enable(xqspi->pclk);
1141 if (ret) {
1142 dev_err(dev, "Unable to enable APB clock.\n");
1143 goto remove_master;
1144 }
1145
1146 ret = clk_prepare_enable(xqspi->refclk);
1147 if (ret) {
1148 dev_err(dev, "Unable to enable device clock.\n");
1149 goto clk_dis_pclk;
1150 }
1151
1152 init_completion(&xqspi->data_completion);
1153
1154 mutex_init(&xqspi->op_lock);
1155
1156 pm_runtime_use_autosuspend(&pdev->dev);
1157 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1158 pm_runtime_set_active(&pdev->dev);
1159 pm_runtime_enable(&pdev->dev);
1160
1161 ret = pm_runtime_get_sync(&pdev->dev);
1162 if (ret < 0) {
1163 dev_err(&pdev->dev, "Failed to pm_runtime_get_sync: %d\n", ret);
1164 goto clk_dis_all;
1165 }
1166
1167 /* QSPI controller initializations */
1168 zynqmp_qspi_init_hw(xqspi);
1169
1170 xqspi->irq = platform_get_irq(pdev, 0);
1171 if (xqspi->irq <= 0) {
1172 ret = -ENXIO;
1173 goto clk_dis_all;
1174 }
1175 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1176 0, pdev->name, xqspi);
1177 if (ret != 0) {
1178 ret = -ENXIO;
1179 dev_err(dev, "request_irq failed\n");
1180 goto clk_dis_all;
1181 }
1182
1183 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
1184 if (ret)
1185 goto clk_dis_all;
1186
1187 ret = of_property_read_u32(np, "num-cs", &num_cs);
1188 if (ret < 0) {
1189 ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1190 } else if (num_cs > GQSPI_MAX_NUM_CS) {
1191 ret = -EINVAL;
1192 dev_err(&pdev->dev, "only %d chip selects are available\n",
1193 GQSPI_MAX_NUM_CS);
1194 goto clk_dis_all;
1195 } else {
1196 ctlr->num_chipselect = num_cs;
1197 }
1198
1199 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1200 ctlr->mem_ops = &zynqmp_qspi_mem_ops;
1201 ctlr->setup = zynqmp_qspi_setup_op;
1202 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1203 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1204 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1205 SPI_TX_DUAL | SPI_TX_QUAD;
1206 ctlr->dev.of_node = np;
1207 ctlr->auto_runtime_pm = true;
1208
1209 ret = devm_spi_register_controller(&pdev->dev, ctlr);
1210 if (ret) {
1211 dev_err(&pdev->dev, "spi_register_controller failed\n");
1212 goto clk_dis_all;
1213 }
1214
1215 pm_runtime_mark_last_busy(&pdev->dev);
1216 pm_runtime_put_autosuspend(&pdev->dev);
1217
1218 return 0;
1219
1220 clk_dis_all:
1221 pm_runtime_put_sync(&pdev->dev);
1222 pm_runtime_set_suspended(&pdev->dev);
1223 pm_runtime_disable(&pdev->dev);
1224 clk_disable_unprepare(xqspi->refclk);
1225 clk_dis_pclk:
1226 clk_disable_unprepare(xqspi->pclk);
1227 remove_master:
1228 spi_controller_put(ctlr);
1229
1230 return ret;
1231 }
1232
1233 /**
1234 * zynqmp_qspi_remove - Remove method for the QSPI driver
1235 * @pdev: Pointer to the platform_device structure
1236 *
1237 * This function is called if a device is physically removed from the system or
1238 * if the driver module is being unloaded. It frees all resources allocated to
1239 * the device.
1240 *
1241 * Return: 0 Always
1242 */
zynqmp_qspi_remove(struct platform_device * pdev)1243 static int zynqmp_qspi_remove(struct platform_device *pdev)
1244 {
1245 struct zynqmp_qspi *xqspi = platform_get_drvdata(pdev);
1246
1247 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1248 clk_disable_unprepare(xqspi->refclk);
1249 clk_disable_unprepare(xqspi->pclk);
1250 pm_runtime_set_suspended(&pdev->dev);
1251 pm_runtime_disable(&pdev->dev);
1252
1253 return 0;
1254 }
1255
1256 static const struct of_device_id zynqmp_qspi_of_match[] = {
1257 { .compatible = "xlnx,zynqmp-qspi-1.0", },
1258 { /* End of table */ }
1259 };
1260
1261 MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1262
1263 static struct platform_driver zynqmp_qspi_driver = {
1264 .probe = zynqmp_qspi_probe,
1265 .remove = zynqmp_qspi_remove,
1266 .driver = {
1267 .name = "zynqmp-qspi",
1268 .of_match_table = zynqmp_qspi_of_match,
1269 .pm = &zynqmp_qspi_dev_pm_ops,
1270 },
1271 };
1272
1273 module_platform_driver(zynqmp_qspi_driver);
1274
1275 MODULE_AUTHOR("Xilinx, Inc.");
1276 MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1277 MODULE_LICENSE("GPL");
1278
