Searched +full:versal +full:- +full:clk (Results 1 – 5 of 5) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Xilinx Versal clock controller10 - Michal Simek <michal.simek@xilinx.com>11 - Jolly Shah <jolly.shah@xilinx.com>12 - Rajan Vaja <rajan.vaja@xilinx.com>15 The clock controller is a hardware block of Xilinx versal clock tree. It23 const: xlnx,versal-clk[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"10 - Adrian Hunter <adrian.hunter@intel.com>13 - $ref: "mmc-controller.yaml#"14 - if:18 const: arasan,sdhci-5.121 - phys22 - phy-names23 - if:[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>9 * Based on sdhci-of-esdhc.c18 #include <linux/clk-provider.h>25 #include <linux/firmware/xlnx-zynqmp.h>28 #include "sdhci-pltfm.h"55 * On some SoCs the syscon area has a feature where the upper 16-bits of56 * each 32-bit register act as a write mask for the lower 16-bits. This allows64 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map68 * @shift: Bit offset within @reg of this field (or -1 if not avail)[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2016-2019 Xilinx7 * Based on drivers/clk/zynq/clkc.c11 #include <linux/clk.h>12 #include <linux/clk-provider.h>18 #include "clk-zynqmp.h"48 * struct clock_parent - Clock parent60 * struct zynqmp_clock - Clock140 * zynqmp_is_valid_clock() - Check whether clock is valid or not148 return -ENODEV; in zynqmp_is_valid_clock()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later5 * Copyright (C) 2009 - 2014 Xilinx, Inc.9 #include <linux/clk.h>20 #define DRIVER_NAME "zynq-gpio"46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)[all …]
