1 // SPDX-License-Identifier: GPL-2.0-or-later
5  * Copyright (C) 2009 - 2014 Xilinx, Inc.
9 #include <linux/clk.h>
20 #define DRIVER_NAME "zynq-gpio"
46 					ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 					ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 					ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 					ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 					ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
61 					ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
64 /* LSW Mask & Data -WO */
66 /* MSW Mask & Data -WO */
68 /* Data Register-RW */
71 /* Direction mode reg-RW */
73 /* Output enable reg-RW */
75 /* Interrupt mask reg-RO */
77 /* Interrupt enable reg-WO */
79 /* Interrupt disable reg-WO */
81 /* Interrupt status reg-RO */
83 /* Interrupt type reg-RW */
85 /* Interrupt polarity reg-RW */
87 /* Interrupt on any, reg-RW */
117  * struct zynq_gpio - gpio device private data structure
120  * @clk:	clock resource for this controller
129 	struct clk *clk;  member
137  * struct zynq_platform_data -  zynq gpio platform data structure
138  * @label:	string to store in gpio->label
158  * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
165 	return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);  in zynq_gpio_is_zynq()
169  * gpio_data_ro_bug - test if HW bug exists or not
176 	return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);  in gpio_data_ro_bug()
180  * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
198 	for (bank = 0; bank < gpio->p_data->max_bank; bank++) {  in zynq_gpio_get_bank_pin()
199 		if ((pin_num >= gpio->p_data->bank_min[bank]) &&  in zynq_gpio_get_bank_pin()
200 		    (pin_num <= gpio->p_data->bank_max[bank])) {  in zynq_gpio_get_bank_pin()
202 			*bank_pin_num = pin_num -  in zynq_gpio_get_bank_pin()
203 					gpio->p_data->bank_min[bank];  in zynq_gpio_get_bank_pin()
206 		if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)  in zynq_gpio_get_bank_pin()
217  * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
236 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
239 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
244 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
247 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
252 		data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
259  * zynq_gpio_set_value - Modify the state of the pin with specified value
266  * gpio pin to the specified value. The state is either 0 or non-zero.
278 		bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;  in zynq_gpio_set_value()
292 	writel_relaxed(state, gpio->base_addr + reg_offset);  in zynq_gpio_set_value()
296  * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
300  * This function uses the read-modify-write sequence to set the direction of
320 		return -EINVAL;  in zynq_gpio_dir_in()
323 	spin_lock_irqsave(&gpio->dirlock, flags);  in zynq_gpio_dir_in()
324 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_in()
326 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_in()
327 	spin_unlock_irqrestore(&gpio->dirlock, flags);  in zynq_gpio_dir_in()
333  * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
355 	spin_lock_irqsave(&gpio->dirlock, flags);  in zynq_gpio_dir_out()
356 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_out()
358 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_out()
361 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));  in zynq_gpio_dir_out()
363 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));  in zynq_gpio_dir_out()
364 	spin_unlock_irqrestore(&gpio->dirlock, flags);  in zynq_gpio_dir_out()
372  * zynq_gpio_get_direction - Read the direction of the specified GPIO pin
388 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_get_direction()
397  * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
410 	device_pin_num = irq_data->hwirq;  in zynq_gpio_irq_mask()
413 		       gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));  in zynq_gpio_irq_mask()
417  * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
431 	device_pin_num = irq_data->hwirq;  in zynq_gpio_irq_unmask()
434 		       gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));  in zynq_gpio_irq_unmask()
438  * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
451 	device_pin_num = irq_data->hwirq;  in zynq_gpio_irq_ack()
454 		       gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));  in zynq_gpio_irq_ack()
458  * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
481  * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
489  * TYPE-EDGE_RISING,  INT_TYPE - 1, INT_POLARITY - 1,  INT_ANY - 0;
490  * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0,  INT_ANY - 0;
491  * TYPE-EDGE_BOTH,    INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
492  * TYPE-LEVEL_HIGH,   INT_TYPE - 0, INT_POLARITY - 1,  INT_ANY - NA;
493  * TYPE-LEVEL_LOW,    INT_TYPE - 0, INT_POLARITY - 0,  INT_ANY - NA
502 	device_pin_num = irq_data->hwirq;  in zynq_gpio_set_irq_type()
505 	int_type = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
507 	int_pol = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
509 	int_any = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
540 		return -EINVAL;  in zynq_gpio_set_irq_type()
544 		       gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
546 		       gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
548 		       gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
567 	irq_set_irq_wake(gpio->irq, on);  in zynq_gpio_set_wake()
577 	ret = pm_runtime_resume_and_get(chip->parent);  in zynq_gpio_irq_reqres()
581 	return gpiochip_reqres_irq(chip, d->hwirq);  in zynq_gpio_irq_reqres()
588 	gpiochip_relres_irq(chip, d->hwirq);  in zynq_gpio_irq_relres()
589 	pm_runtime_put(chip->parent);  in zynq_gpio_irq_relres()
624 	unsigned int bank_offset = gpio->p_data->bank_min[bank_num];  in zynq_gpio_handle_bank_irq()
625 	struct irq_domain *irqdomain = gpio->chip.irq.domain;  in zynq_gpio_handle_bank_irq()
640  * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
659 	for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {  in zynq_gpio_irqhandler()
660 		int_sts = readl_relaxed(gpio->base_addr +  in zynq_gpio_irqhandler()
662 		int_enb = readl_relaxed(gpio->base_addr +  in zynq_gpio_irqhandler()
665 		if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)  in zynq_gpio_irqhandler()
676 	for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {  in zynq_gpio_save_context()
677 		gpio->context.datalsw[bank_num] =  in zynq_gpio_save_context()
678 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
680 		gpio->context.datamsw[bank_num] =  in zynq_gpio_save_context()
681 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
683 		gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
685 		gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
687 		gpio->context.int_type[bank_num] =  in zynq_gpio_save_context()
688 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
690 		gpio->context.int_polarity[bank_num] =  in zynq_gpio_save_context()
691 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
693 		gpio->context.int_any[bank_num] =  in zynq_gpio_save_context()
694 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
696 		if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)  in zynq_gpio_save_context()
705 	for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {  in zynq_gpio_restore_context()
706 		writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +  in zynq_gpio_restore_context()
708 		writel_relaxed(gpio->context.datalsw[bank_num],  in zynq_gpio_restore_context()
709 			       gpio->base_addr +  in zynq_gpio_restore_context()
711 		writel_relaxed(gpio->context.datamsw[bank_num],  in zynq_gpio_restore_context()
712 			       gpio->base_addr +  in zynq_gpio_restore_context()
714 		writel_relaxed(gpio->context.dirm[bank_num],  in zynq_gpio_restore_context()
715 			       gpio->base_addr +  in zynq_gpio_restore_context()
717 		writel_relaxed(gpio->context.int_type[bank_num],  in zynq_gpio_restore_context()
718 			       gpio->base_addr +  in zynq_gpio_restore_context()
720 		writel_relaxed(gpio->context.int_polarity[bank_num],  in zynq_gpio_restore_context()
721 			       gpio->base_addr +  in zynq_gpio_restore_context()
723 		writel_relaxed(gpio->context.int_any[bank_num],  in zynq_gpio_restore_context()
724 			       gpio->base_addr +  in zynq_gpio_restore_context()
726 		writel_relaxed(~(gpio->context.int_en[bank_num]),  in zynq_gpio_restore_context()
727 			       gpio->base_addr +  in zynq_gpio_restore_context()
729 		if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)  in zynq_gpio_restore_context()
737 	struct irq_data *data = irq_get_irq_data(gpio->irq);  in zynq_gpio_suspend()
740 		disable_irq(gpio->irq);  in zynq_gpio_suspend()
753 	struct irq_data *data = irq_get_irq_data(gpio->irq);  in zynq_gpio_resume()
757 		enable_irq(gpio->irq);  in zynq_gpio_resume()
772 	clk_disable_unprepare(gpio->clk);  in zynq_gpio_runtime_suspend()
781 	return clk_prepare_enable(gpio->clk);  in zynq_gpio_runtime_resume()
788 	ret = pm_runtime_get_sync(chip->parent);  in zynq_gpio_request()
799 	pm_runtime_put(chip->parent);  in zynq_gpio_free()
868 	{ .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
869 	{ .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
870 	{ .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
871 	{ .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },
877  * zynq_gpio_probe - Initialization method for a zynq_gpio device
895 	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);  in zynq_gpio_probe()
897 		return -ENOMEM;  in zynq_gpio_probe()
899 	match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);  in zynq_gpio_probe()
901 		dev_err(&pdev->dev, "of_match_node() failed\n");  in zynq_gpio_probe()
902 		return -EINVAL;  in zynq_gpio_probe()
904 	gpio->p_data = match->data;  in zynq_gpio_probe()
907 	gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);  in zynq_gpio_probe()
908 	if (IS_ERR(gpio->base_addr))  in zynq_gpio_probe()
909 		return PTR_ERR(gpio->base_addr);  in zynq_gpio_probe()
911 	gpio->irq = platform_get_irq(pdev, 0);  in zynq_gpio_probe()
912 	if (gpio->irq < 0)  in zynq_gpio_probe()
913 		return gpio->irq;  in zynq_gpio_probe()
916 	chip = &gpio->chip;  in zynq_gpio_probe()
917 	chip->label = gpio->p_data->label;  in zynq_gpio_probe()
918 	chip->owner = THIS_MODULE;  in zynq_gpio_probe()
919 	chip->parent = &pdev->dev;  in zynq_gpio_probe()
920 	chip->get = zynq_gpio_get_value;  in zynq_gpio_probe()
921 	chip->set = zynq_gpio_set_value;  in zynq_gpio_probe()
922 	chip->request = zynq_gpio_request;  in zynq_gpio_probe()
923 	chip->free = zynq_gpio_free;  in zynq_gpio_probe()
924 	chip->direction_input = zynq_gpio_dir_in;  in zynq_gpio_probe()
925 	chip->direction_output = zynq_gpio_dir_out;  in zynq_gpio_probe()
926 	chip->get_direction = zynq_gpio_get_direction;  in zynq_gpio_probe()
927 	chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");  in zynq_gpio_probe()
928 	chip->ngpio = gpio->p_data->ngpio;  in zynq_gpio_probe()
931 	gpio->clk = devm_clk_get(&pdev->dev, NULL);  in zynq_gpio_probe()
932 	if (IS_ERR(gpio->clk))  in zynq_gpio_probe()
933 		return dev_err_probe(&pdev->dev, PTR_ERR(gpio->clk), "input clock not found.\n");  in zynq_gpio_probe()
935 	ret = clk_prepare_enable(gpio->clk);  in zynq_gpio_probe()
937 		dev_err(&pdev->dev, "Unable to enable clock.\n");  in zynq_gpio_probe()
941 	spin_lock_init(&gpio->dirlock);  in zynq_gpio_probe()
943 	pm_runtime_set_active(&pdev->dev);  in zynq_gpio_probe()
944 	pm_runtime_enable(&pdev->dev);  in zynq_gpio_probe()
945 	ret = pm_runtime_resume_and_get(&pdev->dev);  in zynq_gpio_probe()
950 	for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {  in zynq_gpio_probe()
951 		writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +  in zynq_gpio_probe()
953 		if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)  in zynq_gpio_probe()
958 	girq = &chip->irq;  in zynq_gpio_probe()
959 	girq->chip = &zynq_gpio_edge_irqchip;  in zynq_gpio_probe()
960 	girq->parent_handler = zynq_gpio_irqhandler;  in zynq_gpio_probe()
961 	girq->num_parents = 1;  in zynq_gpio_probe()
962 	girq->parents = devm_kcalloc(&pdev->dev, 1,  in zynq_gpio_probe()
963 				     sizeof(*girq->parents),  in zynq_gpio_probe()
965 	if (!girq->parents) {  in zynq_gpio_probe()
966 		ret = -ENOMEM;  in zynq_gpio_probe()
969 	girq->parents[0] = gpio->irq;  in zynq_gpio_probe()
970 	girq->default_type = IRQ_TYPE_NONE;  in zynq_gpio_probe()
971 	girq->handler = handle_level_irq;  in zynq_gpio_probe()
976 		dev_err(&pdev->dev, "Failed to add gpio chip\n");  in zynq_gpio_probe()
980 	irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY);  in zynq_gpio_probe()
981 	device_init_wakeup(&pdev->dev, 1);  in zynq_gpio_probe()
982 	pm_runtime_put(&pdev->dev);  in zynq_gpio_probe()
987 	pm_runtime_put(&pdev->dev);  in zynq_gpio_probe()
989 	pm_runtime_disable(&pdev->dev);  in zynq_gpio_probe()
990 	clk_disable_unprepare(gpio->clk);  in zynq_gpio_probe()
996  * zynq_gpio_remove - Driver removal function
1005 	pm_runtime_get_sync(&pdev->dev);  in zynq_gpio_remove()
1006 	gpiochip_remove(&gpio->chip);  in zynq_gpio_remove()
1007 	clk_disable_unprepare(gpio->clk);  in zynq_gpio_remove()
1008 	device_set_wakeup_capable(&pdev->dev, 0);  in zynq_gpio_remove()
1009 	pm_runtime_disable(&pdev->dev);  in zynq_gpio_remove()
1024  * zynq_gpio_init - Initial driver registration call