1 // SPDX-License-Identifier: GPL-2.0
5  *  Copyright (C) 2016-2019 Xilinx
7  * Based on drivers/clk/zynq/clkc.c
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
18 #include "clk-zynqmp.h"
48  * struct clock_parent - Clock parent
60  * struct zynqmp_clock - Clock
140  * zynqmp_is_valid_clock() - Check whether clock is valid or not
148 		return -ENODEV;  in zynqmp_is_valid_clock()
154  * zynqmp_get_clock_name() - Get name of clock from Clock index
170 	return ret == 0 ? -EINVAL : ret;  in zynqmp_get_clock_name()
174  * zynqmp_get_clock_type() - Get type of clock
190 	return ret == 0 ? -EINVAL : ret;  in zynqmp_get_clock_type()
194  * zynqmp_pm_clock_get_num_clocks() - Get number of clocks in system
216  * zynqmp_pm_clock_get_name() - Get the name of clock for given id
241  * zynqmp_pm_clock_get_topology() - Get the topology of clock for given id
275  * zynqmp_clk_register_fixed_factor() - Register fixed factor with the
308 					  nodes->flag, mult,  in zynqmp_clk_register_fixed_factor()
315  * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
349  * zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id
374  * __zynqmp_clock_get_topology() - Get topology data of clock from firmware
389 	for (i = 0; i < ARRAY_SIZE(response->topology); i++) {  in __zynqmp_clock_get_topology()
390 		type = FIELD_GET(CLK_TOPOLOGY_TYPE, response->topology[i]);  in __zynqmp_clock_get_topology()
395 						   response->topology[i]);  in __zynqmp_clock_get_topology()
398 					  response->topology[i]);  in __zynqmp_clock_get_topology()
401 				  response->topology[i]);  in __zynqmp_clock_get_topology()
409  * zynqmp_clock_get_topology() - Get topology of clock from firmware using
440  * __zynqmp_clock_get_parents() - Get parents info of clock from firmware
455 	for (i = 0; i < ARRAY_SIZE(response->parents); i++) {  in __zynqmp_clock_get_parents()
456 		if (response->parents[i] == NA_PARENT)  in __zynqmp_clock_get_parents()
460 		parent->id = FIELD_GET(CLK_PARENTS_ID, response->parents[i]);  in __zynqmp_clock_get_parents()
461 		if (response->parents[i] == DUMMY_PARENT) {  in __zynqmp_clock_get_parents()
462 			strcpy(parent->name, "dummy_name");  in __zynqmp_clock_get_parents()
463 			parent->flag = 0;  in __zynqmp_clock_get_parents()
465 			parent->flag = FIELD_GET(CLK_PARENTS_FLAGS,  in __zynqmp_clock_get_parents()
466 						 response->parents[i]);  in __zynqmp_clock_get_parents()
467 			if (zynqmp_get_clock_name(parent->id, parent->name))  in __zynqmp_clock_get_parents()
477  * zynqmp_clock_get_parents() - Get parents info from firmware using PM_API
509  * zynqmp_get_parent_list() - Create list of parents name
532 			ret = of_property_match_string(np, "clock-names",  in zynqmp_get_parent_list()
539 			       clk_type_postfix[clk_nodes[parents[i].flag - 1].  in zynqmp_get_parent_list()
550  * zynqmp_register_clk_topology() - Register clock topology
577 		if (j != (num_nodes - 1)) {  in zynqmp_register_clk_topology()
606  * zynqmp_register_clocks() - Register clocks
639 		zynqmp_data->hws[i] =  in zynqmp_register_clocks()
646 		if (IS_ERR(zynqmp_data->hws[i])) {  in zynqmp_register_clocks()
647 			pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n",  in zynqmp_register_clocks()
648 			       clock[i].clk_name, PTR_ERR(zynqmp_data->hws[i]));  in zynqmp_register_clocks()
656  * zynqmp_get_clock_info() - Get clock information from firmware using PM_API
714  * zynqmp_clk_setup() - Setup the clock framework and register clocks
730 		return -ENOMEM;  in zynqmp_clk_setup()
735 		return -ENOMEM;  in zynqmp_clk_setup()
741 	zynqmp_data->num = clock_max_idx;  in zynqmp_clk_setup()
750 	struct device *dev = &pdev->dev;  in zynqmp_clock_probe()
752 	ret = zynqmp_clk_setup(dev->of_node);  in zynqmp_clock_probe()
758 	{.compatible = "xlnx,zynqmp-clk"},
759 	{.compatible = "xlnx,versal-clk"},