Lines Matching +full:versal +full:- +full:clk
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: "mmc-controller.yaml#"
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
28 - xlnx,zynqmp-8.9a
29 - xlnx,versal-8.9a
32 clock-output-names:
34 - items:
35 - const: clk_out_sd0
36 - const: clk_in_sd0
37 - items:
38 - const: clk_out_sd1
39 - const: clk_in_sd1
44 - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
45 - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
46 - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
47 - items:
48 - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
49 - const: arasan,sdhci-5.1
52 arasan,soc-ctl-syscon.
53 - items:
54 - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
55 - const: arasan,sdhci-8.9a
58 clock-output-names and '#clock-cells'.
59 - items:
60 - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
61 - const: arasan,sdhci-8.9a
64 clock-output-names and '#clock-cells'.
65 - items:
66 - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
67 - const: arasan,sdhci-5.1
70 arasan,soc-ctl-syscon.
71 - items:
72 - const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY
73 - const: arasan,sdhci-5.1
76 arasan,soc-ctl-syscon.
77 - items:
78 - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
79 - const: arasan,sdhci-5.1
82 arasan,soc-ctl-syscon.
83 - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller
86 arasan,soc-ctl-syscon.
87 - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller
90 arasan,soc-ctl-syscon.
99 clock-names:
102 - const: clk_xin
103 - const: clk_ahb
104 - const: gate
112 phy-names:
115 arasan,soc-ctl-syscon:
122 clock-output-names:
128 '#clock-cells':
135 xlnx,fails-without-test-cd:
142 xlnx,int-clock-stable-broken:
148 xlnx,mio-bank:
156 clock-output-names: [ '#clock-cells' ]
157 '#clock-cells': [ clock-output-names ]
160 - compatible
161 - reg
162 - interrupts
163 - clocks
164 - clock-names
169 - |
171 compatible = "arasan,sdhci-8.9a";
173 clock-names = "clk_xin", "clk_ahb";
175 interrupt-parent = <&gic>;
179 - |
181 compatible = "arasan,sdhci-5.1";
183 clock-names = "clk_xin", "clk_ahb";
185 interrupt-parent = <&gic>;
188 phy-names = "phy_arasan";
191 - |
192 #include <dt-bindings/clock/rk3399-cru.h>
193 #include <dt-bindings/interrupt-controller/arm-gic.h>
194 #include <dt-bindings/interrupt-controller/irq.h>
196 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
200 clock-names = "clk_xin", "clk_ahb";
201 arasan,soc-ctl-syscon = <&grf>;
202 assigned-clocks = <&cru SCLK_EMMC>;
203 assigned-clock-rates = <200000000>;
204 clock-output-names = "emmc_cardclock";
206 phy-names = "phy_arasan";
207 #clock-cells = <0>;
210 - |
212 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
213 interrupt-parent = <&gic>;
217 clock-names = "clk_xin", "clk_ahb";
218 clock-output-names = "clk_out_sd0", "clk_in_sd0";
219 #clock-cells = <1>;
220 clk-phase-sd-hs = <63>, <72>;
223 - |
225 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
226 interrupt-parent = <&gic>;
230 clock-names = "clk_xin", "clk_ahb";
231 clock-output-names = "clk_out_sd0", "clk_in_sd0";
232 #clock-cells = <1>;
233 clk-phase-sd-hs = <132>, <60>;
236 - |
241 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
243 interrupt-parent = <&ioapic1>;
247 clock-names = "clk_xin", "clk_ahb", "gate";
248 clock-output-names = "emmc_cardclock";
249 #clock-cells = <0>;
251 phy-names = "phy_arasan";
252 arasan,soc-ctl-syscon = <&sysconf>;
255 - |
259 compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
261 interrupt-parent = <&ioapic1>;
265 clock-names = "clk_xin", "clk_ahb", "gate";
266 clock-output-names = "sdxc_cardclock";
267 #clock-cells = <0>;
269 phy-names = "phy_arasan";
270 arasan,soc-ctl-syscon = <&sysconf>;
273 - |
277 compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
280 clock-names = "clk_xin", "clk_ahb";
284 phy-names = "phy_arasan";
285 assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
286 assigned-clock-rates = <200000000>;
287 clock-output-names = "emmc_cardclock";
288 #clock-cells = <0>;
289 arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
292 - |
296 compatible = "intel,keembay-sdhci-5.1-sd";
299 clock-names = "clk_xin", "clk_ahb";
302 arasan,soc-ctl-syscon = <&sd0_phy_syscon>;