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/Linux-v6.1/drivers/clk/analogbits/
Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
32 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
34 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
37 /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
40 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
[all …]
/Linux-v6.1/drivers/video/fbdev/kyro/
DSTG4000InitDevice.c69 #define STG4K3_PLL_MIN_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate */
70 #define STG4K3_PLL_MAX_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate */
71 #define STG4K3_PLL_MINR_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate (restricted) */
72 #define STG4K3_PLL_MAXR_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate (restricted) */
73 #define STG4K3_PLL_MINR_VCO 100000000 /* Min VCO rate (restricted) */
74 #define STG4K3_PLL_MAX_VCO 500000000 /* Max VCO rate */
75 #define STG4K3_PLL_MAXR_VCO 500000000 /* Max VCO rate (restricted) */
101 /* Program SD-RAM interface */ in InitSDRAMRegisters()
129 /* Translate clock in Hz */ in ProgramClock()
130 coreClock *= 100; /* in Hz */ in ProgramClock()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dfsl,plldig.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wen He <wen.he_1@nxp.com>
19 const: fsl,ls1028a-plldig
27 '#clock-cells':
30 fsl,vco-hz:
31 description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
35 its own desired VCO frequency for the PLL.
41 - compatible
[all …]
Dti,lmk04832.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Beguin <liambeguin@gmail.com>
21 - ti,lmk04832
26 '#address-cells':
29 '#size-cells':
32 '#clock-cells':
35 spi-max-frequency:
40 - description: PLL2 reference clock.
[all …]
/Linux-v6.1/drivers/clk/
Dclk-si544.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
45 /* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
74 * struct clk_si544_muldiv - Multiplier/divider settings
79 * If ls_div_bits is non-zero, hs_div must be even
80 * @delta_m: Frequency shift for small -950..+950 ppm changes, 24 bit
93 return regmap_update_bits(data->regmap, SI544_REG_OE_STATE, in si544_enable_output()
117 err = regmap_read(data->regmap, SI544_REG_OE_STATE, &val); in si544_is_prepared()
131 err = regmap_bulk_read(data->regmap, SI544_REG_HS_DIV, reg, 2); in si544_get_muldiv()
135 settings->ls_div_bits = (reg[1] >> 4) & 0x07; in si544_get_muldiv()
[all …]
Dclk-plldig.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
35 /* Range of the VCO frequencies, in Hz */
39 /* Range of the output frequencies, in Hz */
72 val = readl(data->regs + PLLDIG_REG_PLLFM); in plldig_enable()
78 writel(val, data->regs + PLLDIG_REG_PLLFM); in plldig_enable()
88 val = readl(data->regs + PLLDIG_REG_PLLFM); in plldig_disable()
93 writel(val, data->regs + PLLDIG_REG_PLLFM); in plldig_disable()
100 return readl(data->regs + PLLDIG_REG_PLLFM) & in plldig_is_enabled()
110 val = readl(data->regs + PLLDIG_REG_PLLDV); in plldig_recalc_rate()
[all …]
Dclk-lmk04832.c1 // SPDX-License-Identifier: GPL-2.0
3 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
14 #include <linux/clk-provider.h>
24 /* 0x000 - 0x00d System Functions */
36 /* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
77 /* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
126 /* 0x146 - 0x14a CLKin Control */
136 /* 0x14b - 0x152 Holdover */
138 /* 0x153 - 0x15f PLL1 Configuration */
140 /* 0x160 - 0x16e PLL2 Configuration */
[all …]
Dclk-gemini.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "clk-gemini: " fmt
15 #include <linux/clk-provider.h>
21 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/cortina,gemini-reset.h>
23 #include <dt-bindings/clock/cortina,gemini-clock.h>
53 * struct gemini_gate_data - Gemini gated clocks
67 * struct clk_gemini_pci - Gemini PCI clock
79 * struct gemini_reset - gemini reset controller
92 { 1, "security-gate", "secdiv", 0 },
[all …]
/Linux-v6.1/drivers/media/dvb-frontends/
Dstb6100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
74 [STB6100_VCO] = "VCO",
125 .addr = state->config->tuner_address, in stb6100_read_regs()
131 rc = i2c_transfer(state->i2c, &msg, 1); in stb6100_read_regs()
134 state->config->tuner_address, rc); in stb6100_read_regs()
136 return -EREMOTEIO; in stb6100_read_regs()
141 dprintk(verbose, FE_DEBUG, 1, " Read from 0x%02x", state->config->tuner_address); in stb6100_read_regs()
153 .addr = state->config->tuner_address + reg, in stb6100_read_reg()
159 i2c_transfer(state->i2c, &msg, 1); in stb6100_read_reg()
163 return -EINVAL; in stb6100_read_reg()
[all …]
Dstv6110.c1 // SPDX-License-Identifier: GPL-2.0-or-later
43 return a - b; in abssub()
45 return b - a; in abssub()
50 kfree(fe->tuner_priv); in stv6110_release()
51 fe->tuner_priv = NULL; in stv6110_release()
57 struct stv6110_priv *priv = fe->tuner_priv; in stv6110_write_regs()
61 .addr = priv->i2c_address, in stv6110_write_regs()
73 return -EINVAL; in stv6110_write_regs()
77 return -EINVAL; in stv6110_write_regs()
82 if (fe->ops.i2c_gate_ctrl) in stv6110_write_regs()
[all …]
/Linux-v6.1/arch/powerpc/boot/
Dredboot.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 // include/asm-ppc/redboot.h
26 unsigned int bi_intfreq; /* Internal Freq, in Hz */
27 unsigned int bi_busfreq; /* Bus Freq, in Hz */
28 unsigned int bi_cpmfreq; /* CPM Freq, in Hz */
29 unsigned int bi_brgfreq; /* BRG Freq, in Hz */
30 unsigned int bi_vco; /* VCO Out from PLL */
31 unsigned int bi_pci_freq; /* PCI Freq, in Hz */
Dppcboot.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This interface is used for compatibility with old U-boots *ONLY*.
18 * include/asm-ppc/ppcboot.h
48 unsigned long bi_vco; /* VCO Out from PLL, in MHz */
58 unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
59 unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
60 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
84 unsigned int bi_opbfreq; /* OB clock in Hz */
Dppcboot-hotfoot.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This interface is used for compatibility with old U-boots *ONLY*.
11 * least-offensive solution. Please direct all flames to:
13 * Solomon Peachy <solomon@linux-wlan.com>
30 * include/asm-ppc/ppcboot.h
65 unsigned long bi_vco; /* VCO Out from PLL, in MHz */
75 unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
76 unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
77 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
81 unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */
[all …]
/Linux-v6.1/drivers/media/tuners/
Dmax2165.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include "tuner-i2c.h"
38 msg.addr = priv->config->i2c_address; in max2165_write_reg()
43 ret = i2c_transfer(priv->i2c, &msg, 1); in max2165_write_reg()
49 return (ret != 1) ? -EIO : 0; in max2165_write_reg()
55 u8 dev_addr = priv->config->i2c_address; in max2165_read_reg()
64 ret = i2c_transfer(priv->i2c, msg, 2); in max2165_read_reg()
67 return -EIO; in max2165_read_reg()
104 priv->tf_ntch_low_cfg = dat[0] >> 4; in max2165_read_rom_table()
105 priv->tf_ntch_hi_cfg = dat[0] & 0x0F; in max2165_read_rom_table()
[all …]
/Linux-v6.1/drivers/iio/frequency/
Dadf4371.c1 // SPDX-License-Identifier: GPL-2.0
63 #define ADF4371_MAX_OUT_RF8_FREQ ADF4371_MAX_VCO_FREQ /* Hz */
64 #define ADF4371_MIN_OUT_RF8_FREQ (ADF4371_MIN_VCO_FREQ / 64) /* Hz */
65 #define ADF4371_MAX_OUT_RF16_FREQ (ADF4371_MAX_VCO_FREQ * 2) /* Hz */
66 #define ADF4371_MIN_OUT_RF16_FREQ (ADF4371_MIN_VCO_FREQ * 2) /* Hz */
67 #define ADF4371_MAX_OUT_RF32_FREQ (ADF4371_MAX_VCO_FREQ * 4) /* Hz */
68 #define ADF4371_MIN_OUT_RF32_FREQ (ADF4371_MIN_VCO_FREQ * 4) /* Hz */
70 #define ADF4371_MAX_FREQ_PFD 250000000UL /* Hz */
71 #define ADF4371_MAX_FREQ_REFIN 600000000UL /* Hz */
73 /* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */
[all …]
Dadf4350.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2013 Analog Devices Inc.
78 for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) { in adf4350_sync_config()
79 if ((st->regs_hw[i] != st->regs[i]) || in adf4350_sync_config()
88 st->val = cpu_to_be32(st->regs[i] | i); in adf4350_sync_config()
89 ret = spi_write(st->spi, &st->val, 4); in adf4350_sync_config()
92 st->regs_hw[i] = st->regs[i]; in adf4350_sync_config()
93 dev_dbg(&st->spi->dev, "[%d] 0x%X\n", in adf4350_sync_config()
94 i, (u32)st->regs[i] | i); in adf4350_sync_config()
108 return -EINVAL; in adf4350_reg_access()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/iio/frequency/
Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
35 adi,channel-spacing:
38 Channel spacing in Hz (influences MODULUS).
[all …]
/Linux-v6.1/drivers/gpu/drm/bridge/analogix/
Danx7625.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 /* Loading OCM re-trying times */
32 /* Clock frequency in Hz */
149 #define HFP_HBP_DEF ((HBLANKING_MIN - SYNC_LEN_DEF) / 2)
251 #define DPCD_CMD(len, cmd) ((((len) - 1) << LENGTH_SHIFT) | (cmd))
254 /* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */
296 /* Bit[7:6]: VCO band control, only effective */
301 /* Bit[1:0]: test point output select - */
302 /* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */
309 /* Bit[5:4]: VCO metal capacitance - */
[all …]
/Linux-v6.1/drivers/gpu/drm/gma500/
Dgma_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
30 struct drm_device *dev = crtc->dev; in gma_pipe_has_type()
36 if (connector->encoder && connector->encoder->crtc == crtc) { in gma_pipe_has_type()
39 if (gma_encoder->type == type) { in gma_pipe_has_type()
52 /* Wait for 20ms, i.e. one cycle at 50hz. */ in gma_wait_for_vblank()
59 struct drm_device *dev = crtc->dev; in gma_pipe_set_base()
62 struct drm_framebuffer *fb = crtc->primary->fb; in gma_pipe_set_base()
64 int pipe = gma_crtc->pipe; in gma_pipe_set_base()
65 const struct psb_offset *map = &dev_priv->regmap[pipe]; in gma_pipe_set_base()
[all …]
/Linux-v6.1/sound/soc/codecs/
Dnau8825.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
34 #define NUVOTON_CODEC_DAI "nau8825-hifi"
239 * nau8825_sema_acquire - acquire the semaphore of nau88l25
249 * this function returns -ETIME. If the sleep is interrupted by a signal,
250 * this function will return -EINTR. It returns 0 if the semaphore was
262 ret = down_timeout(&nau8825->xtalk_sem, timeout); in nau8825_sema_acquire()
264 dev_warn(nau8825->dev, "Acquire semaphore timeout\n"); in nau8825_sema_acquire()
266 ret = down_trylock(&nau8825->xtalk_sem); in nau8825_sema_acquire()
268 dev_warn(nau8825->dev, "Acquire semaphore fail\n"); in nau8825_sema_acquire()
[all …]
/Linux-v6.1/drivers/gpu/drm/rcar-du/
Drcar_lvds.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car LVDS Encoder
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
13 #include <linux/media-bus-format.h>
52 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
85 iowrite32(data, lvds->mmio + reg); in rcar_lvds_write()
88 /* -----------------------------------------------------------------------------
149 * The LVDS PLL is made of a pre-divider and a multiplier (strangely in rcar_lvds_d3_e3_pll_calc()
150 * enough called M and N respectively), followed by a post-divider E. in rcar_lvds_d3_e3_pll_calc()
152 * ,-----. ,-----. ,-----. ,-----. in rcar_lvds_d3_e3_pll_calc()
[all …]
/Linux-v6.1/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/display/include/
Dgrph_object_ctrl_defs.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
179 uint32_t dp_phy_ref_clk; /* in KHz - DCE12 only */
180 uint32_t i2c_engine_ref_clk; /* in KHz - DCE12 only */
208 uint32_t spread_spectrum_range; /* modulation freq (HZ)*/
212 /* For mem/engine/uvd, Clock Out frequence (VCO ),
263 /* Secondary transmitter configuration for Dual-link DVI */
423 * DFS-bypass flag
431 INVALID_BACKLIGHT = -1
/Linux-v6.1/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c2 * Copyright © 2006-2016 Intel Corporation
40 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
117 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
118 struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
120 shared_dpll[i] = pll->state; in intel_atomic_duplicate_dpll_state()
129 drm_WARN_ON(s->dev, !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex)); in intel_atomic_get_shared_dpll_state()
131 if (!state->dpll_set) { in intel_atomic_get_shared_dpll_state()
132 state->dpll_set = true; in intel_atomic_get_shared_dpll_state()
134 intel_atomic_duplicate_dpll_state(to_i915(s->dev), in intel_atomic_get_shared_dpll_state()
135 state->shared_dpll); in intel_atomic_get_shared_dpll_state()
[all …]
/Linux-v6.1/drivers/clk/bcm/
Dclk-cygnus.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
45 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
105 CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init);
163 CLK_OF_DECLARE(cygnus_lcpll0, "brcm,cygnus-lcpll0", cygnus_lcpll0_clk_init);
166 * MIPI PLL VCO frequency parameter table
169 /* rate (Hz) ndiv_int ndiv_frac pdiv */
242 CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init);
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