1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
35 /* Range of the VCO frequencies, in Hz */
39 /* Range of the output frequencies, in Hz */
72 	val = readl(data->regs + PLLDIG_REG_PLLFM);  in plldig_enable()
78 	writel(val, data->regs + PLLDIG_REG_PLLFM);  in plldig_enable()
88 	val = readl(data->regs + PLLDIG_REG_PLLFM);  in plldig_disable()
93 	writel(val, data->regs + PLLDIG_REG_PLLFM);  in plldig_disable()
100 	return readl(data->regs + PLLDIG_REG_PLLFM) &  in plldig_is_enabled()
110 	val = readl(data->regs + PLLDIG_REG_PLLDV);  in plldig_recalc_rate()
119 	 * If RFDPHI1 has a value of 1 the VCO frequency is also divided by  in plldig_recalc_rate()
125 	return DIV_ROUND_UP(data->vco_freq, rfdphi1);  in plldig_recalc_rate()
145 	req->rate = clamp(req->rate, PHI1_MIN_FREQ, PHI1_MAX_FREQ);  in plldig_determine_rate()
146 	div = plldig_calc_target_div(data->vco_freq, req->rate);  in plldig_determine_rate()
147 	req->rate = DIV_ROUND_UP(data->vco_freq, div);  in plldig_determine_rate()
160 	rfdphi1 = plldig_calc_target_div(data->vco_freq, rate);  in plldig_set_rate()
163 	val = readl(data->regs + PLLDIG_REG_PLLDV);  in plldig_set_rate()
166 	writel(val, data->regs + PLLDIG_REG_PLLDV);  in plldig_set_rate()
172 	return readl_poll_timeout_atomic(data->regs + PLLDIG_REG_PLLSR, cond,  in plldig_set_rate()
196 		return -EINVAL;  in plldig_init()
200 	if (data->vco_freq) {  in plldig_init()
201 		mfd = data->vco_freq / parent_rate;  in plldig_init()
202 		lltmp = data->vco_freq % parent_rate;  in plldig_init()
208 		data->vco_freq = parent_rate * mfd;  in plldig_init()
212 	writel(val, data->regs + PLLDIG_REG_PLLDV);  in plldig_init()
218 		writel(val, data->regs + PLLDIG_REG_PLLFD);  in plldig_init()
227 	struct device *dev = &pdev->dev;  in plldig_clk_probe()
232 		return -ENOMEM;  in plldig_clk_probe()
234 	data->regs = devm_platform_ioremap_resource(pdev, 0);  in plldig_clk_probe()
235 	if (IS_ERR(data->regs))  in plldig_clk_probe()
236 		return PTR_ERR(data->regs);  in plldig_clk_probe()
238 	data->hw.init = CLK_HW_INIT_PARENTS_DATA("dpclk",  in plldig_clk_probe()
243 	ret = devm_clk_hw_register(dev, &data->hw);  in plldig_clk_probe()
246 						dev->of_node->name);  in plldig_clk_probe()
251 					  &data->hw);  in plldig_clk_probe()
258 	 * The frequency of the VCO cannot be changed during runtime.  in plldig_clk_probe()
261 	if (!of_property_read_u32(dev->of_node, "fsl,vco-hz",  in plldig_clk_probe()
262 				  &data->vco_freq)) {  in plldig_clk_probe()
263 		if (data->vco_freq < PLLDIG_MIN_VCO_FREQ ||  in plldig_clk_probe()
264 		    data->vco_freq > PLLDIG_MAX_VCO_FREQ)  in plldig_clk_probe()
265 			return -EINVAL;  in plldig_clk_probe()
268 	return plldig_init(&data->hw);  in plldig_clk_probe()
272 	{ .compatible = "fsl,ls1028a-plldig" },
279 		.name = "plldig-clock",