Lines Matching +full:vco +full:- +full:hz
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
30 struct drm_device *dev = crtc->dev; in gma_pipe_has_type()
36 if (connector->encoder && connector->encoder->crtc == crtc) { in gma_pipe_has_type()
39 if (gma_encoder->type == type) { in gma_pipe_has_type()
52 /* Wait for 20ms, i.e. one cycle at 50hz. */ in gma_wait_for_vblank()
59 struct drm_device *dev = crtc->dev; in gma_pipe_set_base()
62 struct drm_framebuffer *fb = crtc->primary->fb; in gma_pipe_set_base()
64 int pipe = gma_crtc->pipe; in gma_pipe_set_base()
65 const struct psb_offset *map = &dev_priv->regmap[pipe]; in gma_pipe_set_base()
75 dev_err(dev->dev, "No FB bound\n"); in gma_pipe_set_base()
79 pobj = to_psb_gem_object(fb->obj[0]); in gma_pipe_set_base()
86 start = pobj->offset; in gma_pipe_set_base()
87 offset = y * fb->pitches[0] + x * fb->format->cpp[0]; in gma_pipe_set_base()
89 REG_WRITE(map->stride, fb->pitches[0]); in gma_pipe_set_base()
91 dspcntr = REG_READ(map->cntr); in gma_pipe_set_base()
94 switch (fb->format->cpp[0] * 8) { in gma_pipe_set_base()
99 if (fb->format->depth == 15) in gma_pipe_set_base()
109 dev_err(dev->dev, "Unknown color depth\n"); in gma_pipe_set_base()
110 ret = -EINVAL; in gma_pipe_set_base()
113 REG_WRITE(map->cntr, dspcntr); in gma_pipe_set_base()
115 dev_dbg(dev->dev, in gma_pipe_set_base()
119 the linear offset is named base for the other chips. map->surf in gma_pipe_set_base()
120 should be the base and map->linoff the offset for all chips */ in gma_pipe_set_base()
122 REG_WRITE(map->base, offset + start); in gma_pipe_set_base()
123 REG_READ(map->base); in gma_pipe_set_base()
125 REG_WRITE(map->base, offset); in gma_pipe_set_base()
126 REG_READ(map->base); in gma_pipe_set_base()
127 REG_WRITE(map->surf, start); in gma_pipe_set_base()
128 REG_READ(map->surf); in gma_pipe_set_base()
134 psb_gem_unpin(to_psb_gem_object(old_fb->obj[0])); in gma_pipe_set_base()
144 struct drm_device *dev = crtc->dev; in gma_crtc_load_lut()
147 const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe]; in gma_crtc_load_lut()
148 int palreg = map->palette; in gma_crtc_load_lut()
153 if (!crtc->enabled) in gma_crtc_load_lut()
156 r = crtc->gamma_store; in gma_crtc_load_lut()
157 g = r + crtc->gamma_size; in gma_crtc_load_lut()
158 b = g + crtc->gamma_size; in gma_crtc_load_lut()
163 (((*r++ >> 8) + gma_crtc->lut_adj[i]) << 16) | in gma_crtc_load_lut()
164 (((*g++ >> 8) + gma_crtc->lut_adj[i]) << 8) | in gma_crtc_load_lut()
165 ((*b++ >> 8) + gma_crtc->lut_adj[i])); in gma_crtc_load_lut()
170 /* FIXME: Why pipe[0] and not pipe[..._crtc->pipe]? */ in gma_crtc_load_lut()
171 dev_priv->regs.pipe[0].palette[i] = in gma_crtc_load_lut()
172 (((*r++ >> 8) + gma_crtc->lut_adj[i]) << 16) | in gma_crtc_load_lut()
173 (((*g++ >> 8) + gma_crtc->lut_adj[i]) << 8) | in gma_crtc_load_lut()
174 ((*b++ >> 8) + gma_crtc->lut_adj[i]); in gma_crtc_load_lut()
197 struct drm_device *dev = crtc->dev; in gma_crtc_dpms()
200 int pipe = gma_crtc->pipe; in gma_crtc_dpms()
201 const struct psb_offset *map = &dev_priv->regmap[pipe]; in gma_crtc_dpms()
209 dev_priv->ops->disable_sr(dev); in gma_crtc_dpms()
215 if (gma_crtc->active) in gma_crtc_dpms()
218 gma_crtc->active = true; in gma_crtc_dpms()
221 temp = REG_READ(map->dpll); in gma_crtc_dpms()
223 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
224 REG_READ(map->dpll); in gma_crtc_dpms()
227 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
228 REG_READ(map->dpll); in gma_crtc_dpms()
231 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
232 REG_READ(map->dpll); in gma_crtc_dpms()
238 temp = REG_READ(map->cntr); in gma_crtc_dpms()
240 REG_WRITE(map->cntr, in gma_crtc_dpms()
243 REG_WRITE(map->base, REG_READ(map->base)); in gma_crtc_dpms()
249 temp = REG_READ(map->conf); in gma_crtc_dpms()
251 REG_WRITE(map->conf, temp | PIPEACONF_ENABLE); in gma_crtc_dpms()
253 temp = REG_READ(map->status); in gma_crtc_dpms()
256 REG_WRITE(map->status, temp); in gma_crtc_dpms()
257 REG_READ(map->status); in gma_crtc_dpms()
268 if (!gma_crtc->active) in gma_crtc_dpms()
271 gma_crtc->active = false; in gma_crtc_dpms()
287 temp = REG_READ(map->cntr); in gma_crtc_dpms()
289 REG_WRITE(map->cntr, in gma_crtc_dpms()
292 REG_WRITE(map->base, REG_READ(map->base)); in gma_crtc_dpms()
293 REG_READ(map->base); in gma_crtc_dpms()
297 temp = REG_READ(map->conf); in gma_crtc_dpms()
299 REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE); in gma_crtc_dpms()
300 REG_READ(map->conf); in gma_crtc_dpms()
309 temp = REG_READ(map->dpll); in gma_crtc_dpms()
311 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
312 REG_READ(map->dpll); in gma_crtc_dpms()
321 dev_priv->ops->update_wm(dev, crtc); in gma_crtc_dpms()
331 struct drm_device *dev = crtc->dev; in gma_crtc_cursor_set()
334 int pipe = gma_crtc->pipe; in gma_crtc_cursor_set()
340 struct psb_gem_object *cursor_pobj = gma_crtc->cursor_pobj; in gma_crtc_cursor_set()
355 if (gma_crtc->cursor_obj) { in gma_crtc_cursor_set()
356 pobj = to_psb_gem_object(gma_crtc->cursor_obj); in gma_crtc_cursor_set()
358 drm_gem_object_put(gma_crtc->cursor_obj); in gma_crtc_cursor_set()
359 gma_crtc->cursor_obj = NULL; in gma_crtc_cursor_set()
366 dev_dbg(dev->dev, "We currently only support 64x64 cursors\n"); in gma_crtc_cursor_set()
367 return -EINVAL; in gma_crtc_cursor_set()
372 ret = -ENOENT; in gma_crtc_cursor_set()
376 if (obj->size < width * height * 4) { in gma_crtc_cursor_set()
377 dev_dbg(dev->dev, "Buffer is too small\n"); in gma_crtc_cursor_set()
378 ret = -ENOMEM; in gma_crtc_cursor_set()
387 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle); in gma_crtc_cursor_set()
391 if (dev_priv->ops->cursor_needs_phys) { in gma_crtc_cursor_set()
393 dev_err(dev->dev, "No hardware cursor mem available"); in gma_crtc_cursor_set()
394 ret = -ENOMEM; in gma_crtc_cursor_set()
398 cursor_pages = obj->size / PAGE_SIZE; in gma_crtc_cursor_set()
403 tmp_dst = dev_priv->vram_addr + cursor_pobj->offset; in gma_crtc_cursor_set()
405 memcpy_from_page(tmp_dst, pobj->pages[i], 0, PAGE_SIZE); in gma_crtc_cursor_set()
409 addr = gma_crtc->cursor_addr; in gma_crtc_cursor_set()
411 addr = pobj->offset; in gma_crtc_cursor_set()
412 gma_crtc->cursor_addr = addr; in gma_crtc_cursor_set()
427 if (gma_crtc->cursor_obj) { in gma_crtc_cursor_set()
428 pobj = to_psb_gem_object(gma_crtc->cursor_obj); in gma_crtc_cursor_set()
430 drm_gem_object_put(gma_crtc->cursor_obj); in gma_crtc_cursor_set()
433 gma_crtc->cursor_obj = obj; in gma_crtc_cursor_set()
444 struct drm_device *dev = crtc->dev; in gma_crtc_cursor_move()
446 int pipe = gma_crtc->pipe; in gma_crtc_cursor_move()
452 x = -x; in gma_crtc_cursor_move()
456 y = -y; in gma_crtc_cursor_move()
462 addr = gma_crtc->cursor_addr; in gma_crtc_cursor_move()
474 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; in gma_crtc_prepare()
475 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); in gma_crtc_prepare()
480 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; in gma_crtc_commit()
481 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); in gma_crtc_commit()
487 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; in gma_crtc_disable()
489 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); in gma_crtc_disable()
491 if (crtc->primary->fb) { in gma_crtc_disable()
492 pobj = to_psb_gem_object(crtc->primary->fb->obj[0]); in gma_crtc_disable()
501 if (gma_crtc->cursor_pobj) in gma_crtc_destroy()
502 drm_gem_object_put(&gma_crtc->cursor_pobj->base); in gma_crtc_destroy()
504 kfree(gma_crtc->crtc_state); in gma_crtc_destroy()
516 struct drm_framebuffer *current_fb = crtc->primary->fb; in gma_crtc_page_flip()
517 struct drm_framebuffer *old_fb = crtc->primary->old_fb; in gma_crtc_page_flip()
518 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; in gma_crtc_page_flip()
519 struct drm_device *dev = crtc->dev; in gma_crtc_page_flip()
523 if (!crtc_funcs->mode_set_base) in gma_crtc_page_flip()
524 return -EINVAL; in gma_crtc_page_flip()
527 crtc->primary->fb = fb; in gma_crtc_page_flip()
530 spin_lock_irqsave(&dev->event_lock, flags); in gma_crtc_page_flip()
534 gma_crtc->page_flip_event = event; in gma_crtc_page_flip()
535 spin_unlock_irqrestore(&dev->event_lock, flags); in gma_crtc_page_flip()
538 ret = crtc_funcs->mode_set_base(crtc, crtc->x, crtc->y, old_fb); in gma_crtc_page_flip()
540 spin_lock_irqsave(&dev->event_lock, flags); in gma_crtc_page_flip()
541 if (gma_crtc->page_flip_event) { in gma_crtc_page_flip()
542 gma_crtc->page_flip_event = NULL; in gma_crtc_page_flip()
545 spin_unlock_irqrestore(&dev->event_lock, flags); in gma_crtc_page_flip()
548 ret = crtc_funcs->mode_set_base(crtc, crtc->x, crtc->y, old_fb); in gma_crtc_page_flip()
553 crtc->primary->fb = current_fb; in gma_crtc_page_flip()
575 struct drm_device *dev = crtc->dev; in gma_crtc_save()
578 struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; in gma_crtc_save()
579 const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe]; in gma_crtc_save()
584 dev_err(dev->dev, "No CRTC state found\n"); in gma_crtc_save()
588 crtc_state->saveDSPCNTR = REG_READ(map->cntr); in gma_crtc_save()
589 crtc_state->savePIPECONF = REG_READ(map->conf); in gma_crtc_save()
590 crtc_state->savePIPESRC = REG_READ(map->src); in gma_crtc_save()
591 crtc_state->saveFP0 = REG_READ(map->fp0); in gma_crtc_save()
592 crtc_state->saveFP1 = REG_READ(map->fp1); in gma_crtc_save()
593 crtc_state->saveDPLL = REG_READ(map->dpll); in gma_crtc_save()
594 crtc_state->saveHTOTAL = REG_READ(map->htotal); in gma_crtc_save()
595 crtc_state->saveHBLANK = REG_READ(map->hblank); in gma_crtc_save()
596 crtc_state->saveHSYNC = REG_READ(map->hsync); in gma_crtc_save()
597 crtc_state->saveVTOTAL = REG_READ(map->vtotal); in gma_crtc_save()
598 crtc_state->saveVBLANK = REG_READ(map->vblank); in gma_crtc_save()
599 crtc_state->saveVSYNC = REG_READ(map->vsync); in gma_crtc_save()
600 crtc_state->saveDSPSTRIDE = REG_READ(map->stride); in gma_crtc_save()
603 crtc_state->saveDSPSIZE = REG_READ(map->size); in gma_crtc_save()
604 crtc_state->saveDSPPOS = REG_READ(map->pos); in gma_crtc_save()
606 crtc_state->saveDSPBASE = REG_READ(map->base); in gma_crtc_save()
608 palette_reg = map->palette; in gma_crtc_save()
610 crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2)); in gma_crtc_save()
618 struct drm_device *dev = crtc->dev; in gma_crtc_restore()
621 struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; in gma_crtc_restore()
622 const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe]; in gma_crtc_restore()
627 dev_err(dev->dev, "No crtc state\n"); in gma_crtc_restore()
631 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { in gma_crtc_restore()
632 REG_WRITE(map->dpll, in gma_crtc_restore()
633 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); in gma_crtc_restore()
634 REG_READ(map->dpll); in gma_crtc_restore()
638 REG_WRITE(map->fp0, crtc_state->saveFP0); in gma_crtc_restore()
639 REG_READ(map->fp0); in gma_crtc_restore()
641 REG_WRITE(map->fp1, crtc_state->saveFP1); in gma_crtc_restore()
642 REG_READ(map->fp1); in gma_crtc_restore()
644 REG_WRITE(map->dpll, crtc_state->saveDPLL); in gma_crtc_restore()
645 REG_READ(map->dpll); in gma_crtc_restore()
648 REG_WRITE(map->htotal, crtc_state->saveHTOTAL); in gma_crtc_restore()
649 REG_WRITE(map->hblank, crtc_state->saveHBLANK); in gma_crtc_restore()
650 REG_WRITE(map->hsync, crtc_state->saveHSYNC); in gma_crtc_restore()
651 REG_WRITE(map->vtotal, crtc_state->saveVTOTAL); in gma_crtc_restore()
652 REG_WRITE(map->vblank, crtc_state->saveVBLANK); in gma_crtc_restore()
653 REG_WRITE(map->vsync, crtc_state->saveVSYNC); in gma_crtc_restore()
654 REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE); in gma_crtc_restore()
656 REG_WRITE(map->size, crtc_state->saveDSPSIZE); in gma_crtc_restore()
657 REG_WRITE(map->pos, crtc_state->saveDSPPOS); in gma_crtc_restore()
659 REG_WRITE(map->src, crtc_state->savePIPESRC); in gma_crtc_restore()
660 REG_WRITE(map->base, crtc_state->saveDSPBASE); in gma_crtc_restore()
661 REG_WRITE(map->conf, crtc_state->savePIPECONF); in gma_crtc_restore()
665 REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); in gma_crtc_restore()
666 REG_WRITE(map->base, crtc_state->saveDSPBASE); in gma_crtc_restore()
670 palette_reg = map->palette; in gma_crtc_restore()
672 REG_WRITE(palette_reg + (i << 2), crtc_state->savePalette[i]); in gma_crtc_restore()
678 encoder->helper_private; in gma_encoder_prepare()
680 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); in gma_encoder_prepare()
686 encoder->helper_private; in gma_encoder_commit()
688 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); in gma_encoder_commit()
704 return &gma_encoder->base; in gma_best_encoder()
710 connector->encoder = encoder; in gma_connector_attach_encoder()
711 drm_connector_attach_encoder(&connector->base, in gma_connector_attach_encoder()
712 &encoder->base); in gma_connector_attach_encoder()
721 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in gma_pll_is_valid()
723 if (clock->p < limit->p.min || limit->p.max < clock->p) in gma_pll_is_valid()
725 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in gma_pll_is_valid()
727 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in gma_pll_is_valid()
730 if (clock->m1 <= clock->m2 && clock->m1 != 0) in gma_pll_is_valid()
732 if (clock->m < limit->m.min || limit->m.max < clock->m) in gma_pll_is_valid()
734 if (clock->n < limit->n.min || limit->n.max < clock->n) in gma_pll_is_valid()
736 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in gma_pll_is_valid()
737 GMA_PLL_INVALID("vco out of range"); in gma_pll_is_valid()
742 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) in gma_pll_is_valid()
752 struct drm_device *dev = crtc->dev; in gma_find_best_pll()
754 to_gma_crtc(crtc)->clock_funcs; in gma_find_best_pll()
762 * settings for dual-channel. We haven't figured out how to in gma_find_best_pll()
768 clock.p2 = limit->p2.p2_fast; in gma_find_best_pll()
770 clock.p2 = limit->p2.p2_slow; in gma_find_best_pll()
772 if (target < limit->p2.dot_limit) in gma_find_best_pll()
773 clock.p2 = limit->p2.p2_slow; in gma_find_best_pll()
775 clock.p2 = limit->p2.p2_fast; in gma_find_best_pll()
781 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { in gma_find_best_pll()
782 for (clock.m2 = limit->m2.min; in gma_find_best_pll()
784 clock.m2 <= limit->m2.max; clock.m2++) { in gma_find_best_pll()
785 for (clock.n = limit->n.min; in gma_find_best_pll()
786 clock.n <= limit->n.max; clock.n++) { in gma_find_best_pll()
787 for (clock.p1 = limit->p1.min; in gma_find_best_pll()
788 clock.p1 <= limit->p1.max; in gma_find_best_pll()
792 clock_funcs->clock(refclk, &clock); in gma_find_best_pll()
794 if (!clock_funcs->pll_is_valid(crtc, in gma_find_best_pll()
798 this_err = abs(clock.dot - target); in gma_find_best_pll()