| /Linux-v5.4/tools/testing/selftests/kvm/include/ |
| D | evmcs.h | 249 static inline int evmcs_vmptrst(uint64_t *value) in evmcs_vmptrst() argument
251 *value = current_vp_assist->current_nested_vmcs & in evmcs_vmptrst()
257 static inline int evmcs_vmread(uint64_t encoding, uint64_t *value) in evmcs_vmread() argument
261 *value = current_evmcs->guest_rip; in evmcs_vmread()
264 *value = current_evmcs->guest_rsp; in evmcs_vmread()
267 *value = current_evmcs->guest_rflags; in evmcs_vmread()
270 *value = current_evmcs->host_ia32_pat; in evmcs_vmread()
273 *value = current_evmcs->host_ia32_efer; in evmcs_vmread()
276 *value = current_evmcs->host_cr0; in evmcs_vmread()
279 *value = current_evmcs->host_cr3; in evmcs_vmread()
[all …]
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| /Linux-v5.4/drivers/video/fbdev/riva/ |
| D | nvreg.h | 34 #define SetBF(mask,value) ((value) << (0?mask)) argument
37 #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ argument
38 | SetBF(mask,value)))
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
51 #define DEVICE_DEF(device,mask,value) \ argument
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
53 #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) argument
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
59 #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) argument
60 #define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) argument
[all …]
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| /Linux-v5.4/drivers/net/wireless/realtek/rtw88/ |
| D | fw.h | 109 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ argument
110 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0))
111 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ argument
112 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
113 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ argument
114 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16))
115 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ argument
116 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0))
125 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ argument
126 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16))
[all …]
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| D | tx.h | 12 #define SET_TX_DESC_TXPKTSIZE(txdesc, value) \ argument
13 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, GENMASK(15, 0))
14 #define SET_TX_DESC_OFFSET(txdesc, value) \ argument
15 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, GENMASK(23, 16))
16 #define SET_TX_DESC_PKT_OFFSET(txdesc, value) \ argument
17 le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(28, 24))
18 #define SET_TX_DESC_QSEL(txdesc, value) \ argument
19 le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(12, 8))
20 #define SET_TX_DESC_BMC(txdesc, value) \ argument
21 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(24))
[all …]
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_mem_input_v.c | 42 uint32_t value = 0; in set_flip_control() local
44 value = dm_read_reg( in set_flip_control()
48 set_reg_field_value(value, 1, in set_flip_control()
55 value); in set_flip_control()
63 uint32_t value = 0; in program_pri_addr_c() local
69 set_reg_field_value(value, temp, in program_pri_addr_c()
76 value); in program_pri_addr_c()
79 value = 0; in program_pri_addr_c()
83 set_reg_field_value(value, temp, in program_pri_addr_c()
90 value); in program_pri_addr_c()
[all …]
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| D | dce110_opp_regamma_v.c | 39 uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut() local
45 value, in power_on_lut()
51 value, in power_on_lut()
58 value, in power_on_lut()
64 value, in power_on_lut()
70 dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value); in power_on_lut()
73 value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut()
74 if (get_reg_field_value(value, in power_on_lut()
77 get_reg_field_value(value, in power_on_lut()
88 uint32_t value; in set_bypass_input_gamma() local
[all …]
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| D | dce110_opp_csc_v.c | 52 * value = UNDERLAY_SATURATION_MAX /UNDERLAY_SATURATION_DIVIDER
127 uint32_t value = 0; in program_color_matrix_v() local
131 value, in program_color_matrix_v()
137 value, in program_color_matrix_v()
142 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
145 uint32_t value = 0; in program_color_matrix_v() local
149 value, in program_color_matrix_v()
155 value, in program_color_matrix_v()
160 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
163 uint32_t value = 0; in program_color_matrix_v() local
[all …]
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| D | dce110_timing_generator.c | 95 uint32_t value = 0; in dce110_timing_generator_is_in_vertical_blank() local
100 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_is_in_vertical_blank()
101 field = get_reg_field_value(value, CRTC_STATUS, CRTC_V_BLANK); in dce110_timing_generator_is_in_vertical_blank()
128 uint32_t value = 0; in dce110_timing_generator_enable_crtc() local
135 value, in dce110_timing_generator_enable_crtc()
140 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value); in dce110_timing_generator_enable_crtc()
143 value = 0; in dce110_timing_generator_enable_crtc()
144 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK), value); in dce110_timing_generator_enable_crtc()
157 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_program_blank_color() local
160 value, in dce110_timing_generator_program_blank_color()
[all …]
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| D | dce110_timing_generator_v.c | 57 * This is needed for DRR, and also suggested to be default value by Syed. in dce110_timing_generator_v_enable_crtc()
60 uint32_t value; in dce110_timing_generator_v_enable_crtc() local
62 value = 0; in dce110_timing_generator_v_enable_crtc()
63 set_reg_field_value(value, 0, in dce110_timing_generator_v_enable_crtc()
66 mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
69 value = 0; in dce110_timing_generator_v_enable_crtc()
70 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
72 value = 0; in dce110_timing_generator_v_enable_crtc()
73 set_reg_field_value(value, 1, in dce110_timing_generator_v_enable_crtc()
76 mmCRTCV_MASTER_EN, value); in dce110_timing_generator_v_enable_crtc()
[all …]
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| /Linux-v5.4/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwxgmac2_dma.c | 13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset() local
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value, in dwxgmac2_dma_reset()
19 !(value & XGMAC_SWR), 0, 100000); in dwxgmac2_dma_reset()
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init() local
28 value |= XGMAC_AAL; in dwxgmac2_dma_init()
30 writel(value | XGMAC_EAME, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
36 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan() local
39 value |= XGMAC_PBLx8; in dwxgmac2_dma_init_chan()
41 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan()
[all …]
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| D | dwmac4_core.c | 27 u32 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_core_init() local
29 value |= GMAC_CORE_INIT; in dwmac4_core_init()
32 value |= GMAC_CONFIG_TE; in dwmac4_core_init()
34 value &= hw->link.speed_mask; in dwmac4_core_init()
37 value |= hw->link.speed1000; in dwmac4_core_init()
40 value |= hw->link.speed100; in dwmac4_core_init()
43 value |= hw->link.speed10; in dwmac4_core_init()
48 writel(value, ioaddr + GMAC_CONFIG); in dwmac4_core_init()
51 value = GMAC_INT_DEFAULT_ENABLE; in dwmac4_core_init()
54 value |= GMAC_PCS_IRQ_DEFAULT; in dwmac4_core_init()
[all …]
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| D | dwxgmac2_core.c | 69 u32 value; in dwxgmac2_rx_ipc() local
71 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_rx_ipc()
73 value |= XGMAC_CONFIG_IPC; in dwxgmac2_rx_ipc()
75 value &= ~XGMAC_CONFIG_IPC; in dwxgmac2_rx_ipc()
76 writel(value, ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_rx_ipc()
85 u32 value; in dwxgmac2_rx_queue_enable() local
87 value = readl(ioaddr + XGMAC_RXQ_CTRL0) & ~XGMAC_RXQEN(queue); in dwxgmac2_rx_queue_enable()
89 value |= 0x1 << XGMAC_RXQEN_SHIFT(queue); in dwxgmac2_rx_queue_enable()
91 value |= 0x2 << XGMAC_RXQEN_SHIFT(queue); in dwxgmac2_rx_queue_enable()
92 writel(value, ioaddr + XGMAC_RXQ_CTRL0); in dwxgmac2_rx_queue_enable()
[all …]
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| /Linux-v5.4/drivers/media/pci/cx25821/ |
| D | cx25821-medusa-video.c | 24 u32 value = 0; in medusa_enable_bluefield_output() local
63 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); in medusa_enable_bluefield_output()
64 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
66 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
67 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); in medusa_enable_bluefield_output()
69 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); in medusa_enable_bluefield_output()
70 value &= 0xFFFFFF7F; in medusa_enable_bluefield_output()
72 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
73 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); in medusa_enable_bluefield_output()
80 u32 value = 0; in medusa_initialize_ntsc() local
[all …]
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| /Linux-v5.4/drivers/phy/tegra/ |
| D | xusb-tegra210.c | 248 u32 value; in tegra210_pex_uphy_enable() local
264 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
265 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << in tegra210_pex_uphy_enable()
267 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << in tegra210_pex_uphy_enable()
269 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
271 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
272 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << in tegra210_pex_uphy_enable()
274 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << in tegra210_pex_uphy_enable()
276 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
278 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
[all …]
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| D | xusb-tegra124.c | 227 u32 value; in tegra124_xusb_padctl_enable() local
234 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
235 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; in tegra124_xusb_padctl_enable()
236 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
240 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
241 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra124_xusb_padctl_enable()
242 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
246 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
247 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; in tegra124_xusb_padctl_enable()
248 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
[all …]
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| /Linux-v5.4/arch/mips/include/asm/octeon/ |
| D | cvmx-fau.h | 57 * bit will be set. Otherwise the value of the register before
62 int64_t value:63; member
67 * bit will be set. Otherwise the value of the register before
72 int32_t value:31; member
77 * bit will be set. Otherwise the value of the register before
82 int16_t value:15; member
87 * bit will be set. Otherwise the value of the register before
92 int8_t value:7; member
97 * the error bit will be set. Otherwise the value of the
121 * @noadd: 0 = Store value is atomically added to the current value
[all …]
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| /Linux-v5.4/drivers/gpu/drm/bridge/ |
| D | sil-sii8620.h | 15 /* Vendor ID Low byte, default value: 0x01 */
18 /* Vendor ID High byte, default value: 0x00 */
21 /* Device ID Low byte, default value: 0x60 */
24 /* Device ID High byte, default value: 0x86 */
27 /* Device Revision, default value: 0x10 */
30 /* OTP DBYTE510, default value: 0x00 */
33 /* System Control #1, default value: 0x00 */
44 /* System Control DPD, default value: 0x90 */
54 /* Dual link Control, default value: 0x00 */
65 /* PWD Software Reset, default value: 0x20 */
[all …]
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| /Linux-v5.4/tools/power/x86/intel-speed-select/ |
| D | isst-display.c | 79 char *value) in format_and_print_txt() argument
96 if (header && value) { in format_and_print_txt()
98 fprintf(outf, "%s:%s\n", header, value); in format_and_print_txt()
106 static void format_and_print(FILE *outf, int level, char *header, char *value) in format_and_print() argument
113 format_and_print_txt(outf, level, header, value); in format_and_print()
133 if (value) { in format_and_print()
138 fprintf(outf, "\"%s\"", value); in format_and_print()
181 char value[256]; in _isst_pbf_display_information() local
187 snprintf(value, sizeof(value), "%d", in _isst_pbf_display_information()
189 format_and_print(outf, disp_level + 1, header, value); in _isst_pbf_display_information()
[all …]
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| /Linux-v5.4/drivers/gpu/drm/tegra/ |
| D | sor.c | 476 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl() local
478 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
480 return value; in tegra_sor_readl()
483 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
486 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
487 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
525 u32 value; in tegra_clk_sor_pad_set_parent() local
527 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
528 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_clk_sor_pad_set_parent()
532 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_clk_sor_pad_set_parent()
[all …]
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| /Linux-v5.4/drivers/gpu/drm/i915/ |
| D | i915_getparam.c | 15 int value; in i915_getparam_ioctl() local
25 value = i915->drm.pdev->device; in i915_getparam_ioctl()
28 value = i915->drm.pdev->revision; in i915_getparam_ioctl()
31 value = i915->ggtt.num_fences; in i915_getparam_ioctl()
34 value = !!i915->overlay; in i915_getparam_ioctl()
37 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
41 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
45 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
49 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
53 value = HAS_LLC(i915); in i915_getparam_ioctl()
[all …]
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/inc/ |
| D | bw_fixed.h | 33 int64_t value; member
45 return (arg1.value <= arg2.value) ? arg1 : arg2; in bw_min2()
51 return (arg2.value <= arg1.value) ? arg1 : arg2; in bw_max2()
68 struct bw_fixed bw_int_to_fixed_nonconst(int64_t value);
69 static inline struct bw_fixed bw_int_to_fixed(int64_t value) in bw_int_to_fixed() argument
71 if (__builtin_constant_p(value)) { in bw_int_to_fixed()
73 BUILD_BUG_ON(value > BW_FIXED_MAX_I32 || value < BW_FIXED_MIN_I32); in bw_int_to_fixed()
74 res.value = value << BW_FIXED_BITS_PER_FRACTIONAL_PART; in bw_int_to_fixed()
77 return bw_int_to_fixed_nonconst(value); in bw_int_to_fixed()
80 static inline int32_t bw_fixed_to_int(struct bw_fixed value) in bw_fixed_to_int() argument
[all …]
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_audio.c | 54 #define AZ_REG_WRITE(reg_name, value) \ argument
55 write_indirect_azalia_reg(audio, IX_REG(reg_name), value)
79 uint32_t value = 0; in read_indirect_azalia_reg() local
86 value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA); in read_indirect_azalia_reg()
89 reg_index, value); in read_indirect_azalia_reg()
91 return value; in read_indirect_azalia_reg()
297 uint32_t value = 0; in set_high_bit_rate_capable() local
300 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR); in set_high_bit_rate_capable()
302 set_reg_field_value(value, capable, in set_high_bit_rate_capable()
306 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value); in set_high_bit_rate_capable()
[all …]
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/calcs/ |
| D | bw_fixed.c | 49 struct bw_fixed bw_int_to_fixed_nonconst(int64_t value) in bw_int_to_fixed_nonconst() argument
52 ASSERT(value < BW_FIXED_MAX_I32 && value > BW_FIXED_MIN_I32); in bw_int_to_fixed_nonconst()
53 res.value = value << BW_FIXED_BITS_PER_FRACTIONAL_PART; in bw_int_to_fixed_nonconst()
104 res.value = (int64_t)(res_value); in bw_frc_to_fixed()
107 res.value = -res.value; in bw_frc_to_fixed()
118 multiplicand = div64_s64(arg.value, abs_i64(significance.value)); in bw_floor2()
119 result.value = abs_i64(significance.value) * multiplicand; in bw_floor2()
120 ASSERT(abs_i64(result.value) <= abs_i64(arg.value)); in bw_floor2()
131 multiplicand = div64_s64(arg.value, abs_i64(significance.value)); in bw_ceil2()
132 result.value = abs_i64(significance.value) * multiplicand; in bw_ceil2()
[all …]
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| /Linux-v5.4/sound/pci/oxygen/ |
| D | oxygen_mixer.c | 23 info->value.integer.min = chip->model.dac_volume_min; in dac_volume_info()
24 info->value.integer.max = chip->model.dac_volume_max; in dac_volume_info()
29 struct snd_ctl_elem_value *value) in dac_volume_get() argument
36 value->value.integer.value[i] = chip->dac_volume[i]; in dac_volume_get()
42 struct snd_ctl_elem_value *value) in dac_volume_put() argument
51 if (value->value.integer.value[i] != chip->dac_volume[i]) { in dac_volume_put()
52 chip->dac_volume[i] = value->value.integer.value[i]; in dac_volume_put()
62 struct snd_ctl_elem_value *value) in dac_mute_get() argument
67 value->value.integer.value[0] = !chip->dac_mute; in dac_mute_get()
73 struct snd_ctl_elem_value *value) in dac_mute_put() argument
[all …]
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| /Linux-v5.4/include/acpi/ |
| D | acbuffer.h | 30 /* _FDE return value */
41 * _GRT return value
42 * _SRT input value
58 /* _GTM return value */
69 * Formatted _PLD return value. The minimum size is a package containing
122 #define ACPI_PLD_SET_REVISION(dword,value) ACPI_SET_BITS (dword, 0, ACPI_7BIT_MASK, value) /* … argument
125 #define ACPI_PLD_SET_IGNORE_COLOR(dword,value) ACPI_SET_BITS (dword, 7, ACPI_1BIT_MASK, value) /* … argument
128 #define ACPI_PLD_SET_RED(dword,value) ACPI_SET_BITS (dword, 8, ACPI_8BIT_MASK, value) /* … argument
131 #define ACPI_PLD_SET_GREEN(dword,value) ACPI_SET_BITS (dword, 16, ACPI_8BIT_MASK, value) /*… argument
134 #define ACPI_PLD_SET_BLUE(dword,value) ACPI_SET_BITS (dword, 24, ACPI_8BIT_MASK, value) /*… argument
[all …]
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