Lines Matching full:value
248 u32 value; in tegra210_pex_uphy_enable() local
264 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
265 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << in tegra210_pex_uphy_enable()
267 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << in tegra210_pex_uphy_enable()
269 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
271 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
272 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << in tegra210_pex_uphy_enable()
274 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << in tegra210_pex_uphy_enable()
276 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
278 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
279 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; in tegra210_pex_uphy_enable()
280 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
282 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
283 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; in tegra210_pex_uphy_enable()
284 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
286 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
287 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; in tegra210_pex_uphy_enable()
288 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
290 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
291 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK << in tegra210_pex_uphy_enable()
295 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL << in tegra210_pex_uphy_enable()
298 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
300 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
301 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK << in tegra210_pex_uphy_enable()
305 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL << in tegra210_pex_uphy_enable()
307 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
309 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
310 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ; in tegra210_pex_uphy_enable()
311 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
313 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
314 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK << in tegra210_pex_uphy_enable()
316 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
320 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
321 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN; in tegra210_pex_uphy_enable()
322 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
324 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
325 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; in tegra210_pex_uphy_enable()
326 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
331 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
332 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE) in tegra210_pex_uphy_enable()
343 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
344 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; in tegra210_pex_uphy_enable()
345 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
350 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
351 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)) in tegra210_pex_uphy_enable()
362 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
363 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE; in tegra210_pex_uphy_enable()
364 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
369 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
370 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS) in tegra210_pex_uphy_enable()
381 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
382 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN | in tegra210_pex_uphy_enable()
384 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
389 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
390 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE) in tegra210_pex_uphy_enable()
401 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
402 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN; in tegra210_pex_uphy_enable()
403 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
408 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
409 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)) in tegra210_pex_uphy_enable()
420 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
421 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN; in tegra210_pex_uphy_enable()
422 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
426 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
427 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; in tegra210_pex_uphy_enable()
428 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
430 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
431 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; in tegra210_pex_uphy_enable()
432 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
434 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
435 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; in tegra210_pex_uphy_enable()
436 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
477 u32 value; in tegra210_sata_uphy_enable() local
493 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
494 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << in tegra210_sata_uphy_enable()
496 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << in tegra210_sata_uphy_enable()
498 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
500 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL5); in tegra210_sata_uphy_enable()
501 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << in tegra210_sata_uphy_enable()
503 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << in tegra210_sata_uphy_enable()
505 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL5); in tegra210_sata_uphy_enable()
507 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
508 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; in tegra210_sata_uphy_enable()
509 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
511 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
512 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; in tegra210_sata_uphy_enable()
513 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
515 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
516 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; in tegra210_sata_uphy_enable()
517 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
519 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
520 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK << in tegra210_sata_uphy_enable()
524 value |= XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN; in tegra210_sata_uphy_enable()
527 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL << in tegra210_sata_uphy_enable()
530 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL << in tegra210_sata_uphy_enable()
533 value &= ~XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN; in tegra210_sata_uphy_enable()
534 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
536 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
537 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK << in tegra210_sata_uphy_enable()
543 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL << in tegra210_sata_uphy_enable()
546 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL << in tegra210_sata_uphy_enable()
549 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
551 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
552 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ; in tegra210_sata_uphy_enable()
553 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
555 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
556 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK << in tegra210_sata_uphy_enable()
558 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
562 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
563 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN; in tegra210_sata_uphy_enable()
564 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
566 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
567 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; in tegra210_sata_uphy_enable()
568 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
573 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
574 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE) in tegra210_sata_uphy_enable()
585 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
586 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; in tegra210_sata_uphy_enable()
587 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
592 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
593 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)) in tegra210_sata_uphy_enable()
604 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
605 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE; in tegra210_sata_uphy_enable()
606 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
611 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
612 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS) in tegra210_sata_uphy_enable()
623 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
624 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN | in tegra210_sata_uphy_enable()
626 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
631 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
632 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE) in tegra210_sata_uphy_enable()
643 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
644 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN; in tegra210_sata_uphy_enable()
645 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
650 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
651 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)) in tegra210_sata_uphy_enable()
662 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
663 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN; in tegra210_sata_uphy_enable()
664 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
668 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
669 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; in tegra210_sata_uphy_enable()
670 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
672 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
673 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; in tegra210_sata_uphy_enable()
674 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
676 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
677 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; in tegra210_sata_uphy_enable()
678 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
716 u32 value; in tegra210_xusb_padctl_enable() local
723 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
724 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN; in tegra210_xusb_padctl_enable()
725 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
729 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
730 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra210_xusb_padctl_enable()
731 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
735 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
736 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN; in tegra210_xusb_padctl_enable()
737 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
746 u32 value; in tegra210_xusb_padctl_disable() local
756 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
757 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN; in tegra210_xusb_padctl_disable()
758 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
762 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
763 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra210_xusb_padctl_disable()
764 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
768 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
769 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN; in tegra210_xusb_padctl_disable()
770 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
780 u32 value; in tegra210_hsic_set_idle() local
782 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_set_idle()
784 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 | in tegra210_hsic_set_idle()
789 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | in tegra210_hsic_set_idle()
793 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | in tegra210_hsic_set_idle()
797 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_set_idle()
807 u32 value, offset; in tegra210_usb3_set_lfps_detect() local
820 value = padctl_readl(padctl, offset); in tegra210_usb3_set_lfps_detect()
822 value &= ~((XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK << in tegra210_usb3_set_lfps_detect()
828 value |= (XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL << in tegra210_usb3_set_lfps_detect()
834 padctl_writel(padctl, value, offset); in tegra210_usb3_set_lfps_detect()
904 u32 value; in tegra210_usb2_phy_init() local
906 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_usb2_phy_init()
907 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK << in tegra210_usb2_phy_init()
909 value |= XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB << in tegra210_usb2_phy_init()
911 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_usb2_phy_init()
932 u32 value; in tegra210_usb2_phy_power_on() local
943 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
944 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK << in tegra210_usb2_phy_power_on()
948 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL << in tegra210_usb2_phy_power_on()
952 value |= in tegra210_usb2_phy_power_on()
956 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
958 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP); in tegra210_usb2_phy_power_on()
959 value &= ~XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(index); in tegra210_usb2_phy_power_on()
960 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index); in tegra210_usb2_phy_power_on()
961 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP); in tegra210_usb2_phy_power_on()
963 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra210_usb2_phy_power_on()
964 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK << in tegra210_usb2_phy_power_on()
969 value |= (priv->fuse.hs_curr_level[index] + in tegra210_usb2_phy_power_on()
972 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra210_usb2_phy_power_on()
974 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra210_usb2_phy_power_on()
975 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK << in tegra210_usb2_phy_power_on()
982 value |= (priv->fuse.hs_term_range_adj << in tegra210_usb2_phy_power_on()
986 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra210_usb2_phy_power_on()
988 value = padctl_readl(padctl, in tegra210_usb2_phy_power_on()
990 value &= ~(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK << in tegra210_usb2_phy_power_on()
992 value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18; in tegra210_usb2_phy_power_on()
993 padctl_writel(padctl, value, in tegra210_usb2_phy_power_on()
1012 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1013 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK << in tegra210_usb2_phy_power_on()
1017 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL << in tegra210_usb2_phy_power_on()
1021 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1023 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
1024 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD; in tegra210_usb2_phy_power_on()
1025 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
1029 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1030 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK; in tegra210_usb2_phy_power_on()
1031 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1054 u32 value; in tegra210_usb2_phy_power_off() local
1071 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_off()
1072 value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD; in tegra210_usb2_phy_power_off()
1073 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_off()
1203 u32 value; in tegra210_hsic_phy_init() local
1205 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_hsic_phy_init()
1206 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK << in tegra210_hsic_phy_init()
1208 value |= XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB << in tegra210_hsic_phy_init()
1210 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_hsic_phy_init()
1230 u32 value; in tegra210_hsic_phy_power_on() local
1242 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_on()
1243 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK << in tegra210_hsic_phy_power_on()
1245 value |= (hsic->tx_rtune_p << in tegra210_hsic_phy_power_on()
1247 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_on()
1249 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index)); in tegra210_hsic_phy_power_on()
1250 value &= ~((XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK << in tegra210_hsic_phy_power_on()
1254 value |= (hsic->rx_strobe_trim << in tegra210_hsic_phy_power_on()
1258 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index)); in tegra210_hsic_phy_power_on()
1260 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_on()
1261 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 | in tegra210_hsic_phy_power_on()
1273 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | in tegra210_hsic_phy_power_on()
1276 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_on()
1282 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1283 value &= ~((XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK << in tegra210_hsic_phy_power_on()
1287 value |= (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL << in tegra210_hsic_phy_power_on()
1291 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1295 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1296 value &= ~XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK; in tegra210_hsic_phy_power_on()
1297 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1316 u32 value; in tegra210_hsic_phy_power_off() local
1318 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_off()
1319 value |= XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 | in tegra210_hsic_phy_power_off()
1328 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_off()
1479 u32 value; in tegra210_pcie_phy_power_on() local
1488 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_on()
1489 value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); in tegra210_pcie_phy_power_on()
1490 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_on()
1501 u32 value; in tegra210_pcie_phy_power_off() local
1503 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_off()
1504 value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); in tegra210_pcie_phy_power_off()
1505 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_off()
1650 u32 value; in tegra210_sata_phy_power_on() local
1659 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_on()
1660 value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); in tegra210_sata_phy_power_on()
1661 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_on()
1672 u32 value; in tegra210_sata_phy_power_off() local
1674 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_off()
1675 value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); in tegra210_sata_phy_power_off()
1676 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_off()
1809 u32 value; in tegra210_usb3_port_enable() local
1812 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_enable()
1815 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index); in tegra210_usb3_port_enable()
1817 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index); in tegra210_usb3_port_enable()
1819 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index); in tegra210_usb3_port_enable()
1820 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port); in tegra210_usb3_port_enable()
1821 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_enable()
1832 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); in tegra210_usb3_port_enable()
1833 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK << in tegra210_usb3_port_enable()
1835 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL << in tegra210_usb3_port_enable()
1837 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); in tegra210_usb3_port_enable()
1839 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); in tegra210_usb3_port_enable()
1840 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK << in tegra210_usb3_port_enable()
1842 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL << in tegra210_usb3_port_enable()
1844 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); in tegra210_usb3_port_enable()
1849 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); in tegra210_usb3_port_enable()
1850 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK << in tegra210_usb3_port_enable()
1852 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL << in tegra210_usb3_port_enable()
1854 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); in tegra210_usb3_port_enable()
1870 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1871 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index); in tegra210_usb3_port_enable()
1872 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1876 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1877 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index); in tegra210_usb3_port_enable()
1878 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1882 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1883 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index); in tegra210_usb3_port_enable()
1884 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
1895 u32 value; in tegra210_usb3_port_disable() local
1897 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1898 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index); in tegra210_usb3_port_disable()
1899 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1903 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1904 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index); in tegra210_usb3_port_disable()
1905 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1909 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1910 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index); in tegra210_usb3_port_disable()
1911 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
1920 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_disable()
1921 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index); in tegra210_usb3_port_disable()
1922 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, 0x7); in tegra210_usb3_port_disable()
1923 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_disable()
1952 u32 value; in tegra210_xusb_read_fuse_calibration() local
1955 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value); in tegra210_xusb_read_fuse_calibration()
1961 (value >> FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(i)) & in tegra210_xusb_read_fuse_calibration()
1966 (value >> FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT) & in tegra210_xusb_read_fuse_calibration()
1969 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value); in tegra210_xusb_read_fuse_calibration()
1974 (value >> FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT) & in tegra210_xusb_read_fuse_calibration()