Lines Matching full:value
476 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl() local
478 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
480 return value; in tegra_sor_readl()
483 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
486 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
487 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
525 u32 value; in tegra_clk_sor_pad_set_parent() local
527 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
528 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_clk_sor_pad_set_parent()
532 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_clk_sor_pad_set_parent()
536 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_clk_sor_pad_set_parent()
540 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
550 u32 value; in tegra_clk_sor_pad_get_parent() local
552 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_get_parent()
554 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { in tegra_clk_sor_pad_get_parent()
605 u32 value; in tegra_sor_dp_train_fast() local
609 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | in tegra_sor_dp_train_fast()
613 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_dp_train_fast()
615 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | in tegra_sor_dp_train_fast()
619 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_dp_train_fast()
621 value = SOR_LANE_POSTCURSOR_LANE3(0x00) | in tegra_sor_dp_train_fast()
625 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); in tegra_sor_dp_train_fast()
630 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
631 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_dp_train_fast()
632 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_dp_train_fast()
633 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ in tegra_sor_dp_train_fast()
634 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
636 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
637 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | in tegra_sor_dp_train_fast()
639 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
643 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
644 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | in tegra_sor_dp_train_fast()
646 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
652 for (i = 0, value = 0; i < link->num_lanes; i++) { in tegra_sor_dp_train_fast()
656 value = (value << 8) | lane; in tegra_sor_dp_train_fast()
659 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
667 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_train_fast()
668 value |= SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_dp_train_fast()
669 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_train_fast()
670 value |= SOR_DP_SPARE_MACRO_SOR_CLK; in tegra_sor_dp_train_fast()
671 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_train_fast()
673 for (i = 0, value = 0; i < link->num_lanes; i++) { in tegra_sor_dp_train_fast()
677 value = (value << 8) | lane; in tegra_sor_dp_train_fast()
680 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
688 for (i = 0, value = 0; i < link->num_lanes; i++) { in tegra_sor_dp_train_fast()
692 value = (value << 8) | lane; in tegra_sor_dp_train_fast()
695 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
722 u32 value; in tegra_sor_setup_pwm() local
724 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
725 value &= ~SOR_PWM_DIV_MASK; in tegra_sor_setup_pwm()
726 value |= 0x400; /* period */ in tegra_sor_setup_pwm()
727 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
729 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
730 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; in tegra_sor_setup_pwm()
731 value |= 0x400; /* duty cycle */ in tegra_sor_setup_pwm()
732 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ in tegra_sor_setup_pwm()
733 value |= SOR_PWM_CTL_TRIGGER; in tegra_sor_setup_pwm()
734 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
739 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
740 if ((value & SOR_PWM_CTL_TRIGGER) == 0) in tegra_sor_setup_pwm()
751 unsigned long value, timeout; in tegra_sor_attach() local
754 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
755 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; in tegra_sor_attach()
756 value |= SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_attach()
757 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
761 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
762 value |= SOR_SUPER_STATE_ATTACHED; in tegra_sor_attach()
763 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
769 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
770 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_attach()
781 unsigned long value, timeout; in tegra_sor_wakeup() local
787 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
788 value &= SOR_TEST_HEAD_MODE_MASK; in tegra_sor_wakeup()
790 if (value == SOR_TEST_HEAD_MODE_AWAKE) in tegra_sor_wakeup()
801 u32 value; in tegra_sor_power_up() local
803 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
804 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_up()
805 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
810 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
811 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_up()
998 u32 value; in tegra_sor_apply_config() local
1000 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1001 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; in tegra_sor_apply_config()
1002 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); in tegra_sor_apply_config()
1003 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1005 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1006 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; in tegra_sor_apply_config()
1007 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); in tegra_sor_apply_config()
1009 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; in tegra_sor_apply_config()
1010 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); in tegra_sor_apply_config()
1012 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; in tegra_sor_apply_config()
1013 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); in tegra_sor_apply_config()
1016 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_apply_config()
1018 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_apply_config()
1020 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; in tegra_sor_apply_config()
1021 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; in tegra_sor_apply_config()
1022 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1024 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1025 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; in tegra_sor_apply_config()
1026 value |= config->hblank_symbols & 0xffff; in tegra_sor_apply_config()
1027 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1029 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1030 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; in tegra_sor_apply_config()
1031 value |= config->vblank_symbols & 0xffff; in tegra_sor_apply_config()
1032 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1041 u32 value; in tegra_sor_mode_set() local
1043 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_mode_set()
1044 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; in tegra_sor_mode_set()
1045 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_mode_set()
1046 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_mode_set()
1048 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | in tegra_sor_mode_set()
1052 value &= ~SOR_STATE_ASY_HSYNCPOL; in tegra_sor_mode_set()
1055 value |= SOR_STATE_ASY_HSYNCPOL; in tegra_sor_mode_set()
1058 value &= ~SOR_STATE_ASY_VSYNCPOL; in tegra_sor_mode_set()
1061 value |= SOR_STATE_ASY_VSYNCPOL; in tegra_sor_mode_set()
1065 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; in tegra_sor_mode_set()
1069 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; in tegra_sor_mode_set()
1073 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; in tegra_sor_mode_set()
1077 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_mode_set()
1081 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; in tegra_sor_mode_set()
1085 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_mode_set()
1089 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_mode_set()
1096 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); in tegra_sor_mode_set()
1097 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1103 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); in tegra_sor_mode_set()
1104 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1110 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); in tegra_sor_mode_set()
1111 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1117 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); in tegra_sor_mode_set()
1118 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1126 unsigned long value, timeout; in tegra_sor_detach() local
1129 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1130 value &= ~SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_detach()
1131 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1137 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
1138 if (value & SOR_PWR_MODE_SAFE) in tegra_sor_detach()
1142 if ((value & SOR_PWR_MODE_SAFE) == 0) in tegra_sor_detach()
1146 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1147 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; in tegra_sor_detach()
1148 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1152 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1153 value &= ~SOR_SUPER_STATE_ATTACHED; in tegra_sor_detach()
1154 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1160 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
1161 if ((value & SOR_TEST_ATTACHED) == 0) in tegra_sor_detach()
1167 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_detach()
1175 unsigned long value, timeout; in tegra_sor_power_down() local
1178 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1179 value &= ~SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_down()
1180 value |= SOR_PWR_TRIGGER; in tegra_sor_power_down()
1181 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
1186 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1187 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_down()
1193 if ((value & SOR_PWR_TRIGGER) != 0) in tegra_sor_power_down()
1203 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down()
1204 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_power_down()
1206 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down()
1209 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | in tegra_sor_power_down()
1211 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
1216 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
1217 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_down()
1223 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_down()
1226 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1227 value |= SOR_PLL2_PORT_POWERDOWN; in tegra_sor_power_down()
1228 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1232 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1233 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; in tegra_sor_power_down()
1234 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1236 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1237 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_power_down()
1238 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_power_down()
1239 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1248 u32 value; in tegra_sor_crc_wait() local
1253 value = tegra_sor_readl(sor, SOR_CRCA); in tegra_sor_crc_wait()
1254 if (value & SOR_CRCA_VALID) in tegra_sor_crc_wait()
1270 u32 value; in tegra_sor_show_crc() local
1279 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_show_crc()
1280 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_show_crc()
1281 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
1283 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1284 value |= SOR_CRC_CNTRL_ENABLE; in tegra_sor_show_crc()
1285 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1287 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_show_crc()
1288 value &= ~SOR_TEST_CRC_POST_SERIALIZE; in tegra_sor_show_crc()
1289 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
1296 value = tegra_sor_readl(sor, SOR_CRCB); in tegra_sor_show_crc()
1298 seq_printf(s, "%08x\n", value); in tegra_sor_show_crc()
1592 u32 value; in tegra_sor_edp_disable() local
1610 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_disable()
1611 value &= ~SOR_ENABLE(0); in tegra_sor_edp_disable()
1612 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_disable()
1639 unsigned int *value)
1668 if (value) {
1670 *value = a + 1;
1672 *value = a;
1691 u32 value; in tegra_sor_edp_enable() local
1722 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1723 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_edp_enable()
1724 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_sor_edp_enable()
1725 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1727 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1728 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_edp_enable()
1729 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1732 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_edp_enable()
1733 value |= SOR_PLL3_PLL_VDD_MODE_3V3; in tegra_sor_edp_enable()
1734 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_edp_enable()
1736 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST | in tegra_sor_edp_enable()
1738 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1740 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1741 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_edp_enable()
1742 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_edp_enable()
1743 value |= SOR_PLL2_LVDS_ENABLE; in tegra_sor_edp_enable()
1744 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1746 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM; in tegra_sor_edp_enable()
1747 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_edp_enable()
1750 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1751 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0) in tegra_sor_edp_enable()
1757 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1758 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; in tegra_sor_edp_enable()
1759 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_edp_enable()
1760 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1767 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1768 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_edp_enable()
1769 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; in tegra_sor_edp_enable()
1770 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1773 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1774 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN | in tegra_sor_edp_enable()
1776 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1778 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1779 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; in tegra_sor_edp_enable()
1780 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1782 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1783 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_edp_enable()
1784 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1794 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1795 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_edp_enable()
1796 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1801 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1802 value &= ~SOR_PLL0_VCOPD; in tegra_sor_edp_enable()
1803 value &= ~SOR_PLL0_PWR; in tegra_sor_edp_enable()
1804 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1806 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1807 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_edp_enable()
1808 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1813 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1814 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_edp_enable()
1815 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1818 for (value = 0, i = 0; i < 5; i++) in tegra_sor_edp_enable()
1819 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | in tegra_sor_edp_enable()
1823 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_edp_enable()
1831 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1834 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); in tegra_sor_edp_enable()
1836 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2; in tegra_sor_edp_enable()
1839 value &= ~SOR_DP_PADCTL_PD_TXD_1; in tegra_sor_edp_enable()
1841 value |= SOR_DP_PADCTL_PD_TXD_1; in tegra_sor_edp_enable()
1844 value &= ~SOR_DP_PADCTL_PD_TXD_0; in tegra_sor_edp_enable()
1846 value |= SOR_DP_PADCTL_PD_TXD_0; in tegra_sor_edp_enable()
1848 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1850 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1851 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_edp_enable()
1852 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes); in tegra_sor_edp_enable()
1853 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1856 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_edp_enable()
1858 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_edp_enable()
1861 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_edp_enable()
1862 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_edp_enable()
1869 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1870 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_edp_enable()
1871 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; in tegra_sor_edp_enable()
1872 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1877 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1878 value |= SOR_DP_LINKCTL_ENABLE; in tegra_sor_edp_enable()
1879 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; in tegra_sor_edp_enable()
1880 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1882 for (i = 0, value = 0; i < 4; i++) { in tegra_sor_edp_enable()
1886 value = (value << 8) | lane; in tegra_sor_edp_enable()
1889 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_edp_enable()
1892 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1893 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_edp_enable()
1894 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1911 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1912 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_edp_enable()
1913 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); in tegra_sor_edp_enable()
1914 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1916 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1917 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_edp_enable()
1918 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); in tegra_sor_edp_enable()
1921 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; in tegra_sor_edp_enable()
1923 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1931 value = (value << 8) | lane; in tegra_sor_edp_enable()
1934 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_edp_enable()
1947 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | in tegra_sor_edp_enable()
1949 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_edp_enable()
1952 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_edp_enable()
1953 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_edp_enable()
1954 value |= SOR_STATE_ASY_PROTOCOL_DP_A; in tegra_sor_edp_enable()
1955 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_edp_enable()
1966 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_enable()
1967 value |= SOR_ENABLE(0); in tegra_sor_edp_enable()
1968 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_enable()
2041 u32 value = 0; in tegra_sor_hdmi_subpack() local
2045 value = (value << 8) | ptr[i - 1]; in tegra_sor_hdmi_subpack()
2047 return value; in tegra_sor_hdmi_subpack()
2056 u32 value; in tegra_sor_hdmi_write_infopack() local
2077 value = INFOFRAME_HEADER_TYPE(ptr[0]) | in tegra_sor_hdmi_write_infopack()
2080 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
2091 value = tegra_sor_hdmi_subpack(&ptr[i], num); in tegra_sor_hdmi_write_infopack()
2092 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
2096 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); in tegra_sor_hdmi_write_infopack()
2097 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
2107 u32 value; in tegra_sor_hdmi_setup_avi_infoframe() local
2111 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2112 value &= ~INFOFRAME_CTRL_SINGLE; in tegra_sor_hdmi_setup_avi_infoframe()
2113 value &= ~INFOFRAME_CTRL_OTHER; in tegra_sor_hdmi_setup_avi_infoframe()
2114 value &= ~INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
2115 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2133 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2134 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
2135 value |= INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
2136 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2161 u32 value; in tegra_sor_audio_prepare() local
2165 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD; in tegra_sor_audio_prepare()
2166 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_prepare()
2178 u32 value; in tegra_sor_hdmi_enable_audio_infoframe() local
2197 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2198 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; in tegra_sor_hdmi_enable_audio_infoframe()
2199 value |= INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_enable_audio_infoframe()
2200 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2207 u32 value; in tegra_sor_hdmi_audio_enable() local
2209 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); in tegra_sor_hdmi_audio_enable()
2212 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK); in tegra_sor_hdmi_audio_enable()
2213 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA); in tegra_sor_hdmi_audio_enable()
2217 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL; in tegra_sor_hdmi_audio_enable()
2219 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL; in tegra_sor_hdmi_audio_enable()
2221 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH; in tegra_sor_hdmi_audio_enable()
2223 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); in tegra_sor_hdmi_audio_enable()
2230 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH | in tegra_sor_hdmi_audio_enable()
2233 tegra_sor_writel(sor, value, SOR_HDMI_SPARE); in tegra_sor_hdmi_audio_enable()
2236 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0); in tegra_sor_hdmi_audio_enable()
2237 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); in tegra_sor_hdmi_audio_enable()
2240 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE; in tegra_sor_hdmi_audio_enable()
2241 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); in tegra_sor_hdmi_audio_enable()
2244 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP; in tegra_sor_hdmi_audio_enable()
2245 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2247 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2248 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); in tegra_sor_hdmi_audio_enable()
2260 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2261 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); in tegra_sor_hdmi_audio_enable()
2264 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2265 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); in tegra_sor_hdmi_audio_enable()
2268 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2269 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); in tegra_sor_hdmi_audio_enable()
2272 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2273 value &= ~SOR_HDMI_AUDIO_N_RESET; in tegra_sor_hdmi_audio_enable()
2274 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2281 u32 value; in tegra_sor_hdmi_disable_audio_infoframe() local
2283 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2284 value &= ~INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_disable_audio_infoframe()
2285 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2307 u32 value; in tegra_sor_hdmi_disable_scrambling() local
2309 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2310 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; in tegra_sor_hdmi_disable_scrambling()
2311 value &= ~SOR_HDMI2_CTRL_SCRAMBLE; in tegra_sor_hdmi_disable_scrambling()
2312 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2335 u32 value; in tegra_sor_hdmi_enable_scrambling() local
2337 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2338 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; in tegra_sor_hdmi_enable_scrambling()
2339 value |= SOR_HDMI2_CTRL_SCRAMBLE; in tegra_sor_hdmi_enable_scrambling()
2340 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2385 u32 value; in tegra_sor_hdmi_disable() local
2399 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2402 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1)); in tegra_sor_hdmi_disable()
2404 value &= ~SOR_ENABLE(sor->index); in tegra_sor_hdmi_disable()
2406 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2432 u32 value; in tegra_sor_hdmi_enable() local
2456 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2457 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_hdmi_enable()
2458 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2462 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2463 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; in tegra_sor_hdmi_enable()
2464 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2466 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2467 value &= ~SOR_PLL0_VCOPD; in tegra_sor_hdmi_enable()
2468 value &= ~SOR_PLL0_PWR; in tegra_sor_hdmi_enable()
2469 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2471 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2472 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_hdmi_enable()
2473 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2477 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2478 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; in tegra_sor_hdmi_enable()
2479 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_hdmi_enable()
2480 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2484 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2485 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_hdmi_enable()
2487 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2490 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2491 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) in tegra_sor_hdmi_enable()
2497 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_hdmi_enable()
2499 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2502 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2503 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_hdmi_enable()
2509 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2510 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_hdmi_enable()
2511 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_hdmi_enable()
2515 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; in tegra_sor_hdmi_enable()
2518 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; in tegra_sor_hdmi_enable()
2521 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_sor_hdmi_enable()
2522 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2527 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2528 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_hdmi_enable()
2529 value |= SOR_DP_LINKCTL_LANE_COUNT(4); in tegra_sor_hdmi_enable()
2530 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2532 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2533 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; in tegra_sor_hdmi_enable()
2534 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_hdmi_enable()
2535 value &= ~SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_hdmi_enable()
2536 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK; in tegra_sor_hdmi_enable()
2537 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2539 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | in tegra_sor_hdmi_enable()
2541 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
2543 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | in tegra_sor_hdmi_enable()
2545 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
2546 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
2550 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); in tegra_sor_hdmi_enable()
2551 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
2555 for (value = 0, i = 0; i < 5; i++) in tegra_sor_hdmi_enable()
2556 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | in tegra_sor_hdmi_enable()
2560 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
2586 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); in tegra_sor_hdmi_enable()
2590 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; in tegra_sor_hdmi_enable()
2592 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
2597 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | in tegra_sor_hdmi_enable()
2599 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
2607 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | in tegra_sor_hdmi_enable()
2609 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_sor_hdmi_enable()
2611 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); in tegra_sor_hdmi_enable()
2612 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_sor_hdmi_enable()
2614 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2615 value |= H_PULSE2_ENABLE; in tegra_sor_hdmi_enable()
2616 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2628 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2629 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_hdmi_enable()
2630 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; in tegra_sor_hdmi_enable()
2631 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2634 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2635 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
2636 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2646 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2647 value &= ~SOR_PLL0_ICHPMP_MASK; in tegra_sor_hdmi_enable()
2648 value &= ~SOR_PLL0_FILTER_MASK; in tegra_sor_hdmi_enable()
2649 value &= ~SOR_PLL0_VCOCAP_MASK; in tegra_sor_hdmi_enable()
2650 value |= SOR_PLL0_ICHPMP(settings->ichpmp); in tegra_sor_hdmi_enable()
2651 value |= SOR_PLL0_FILTER(settings->filter); in tegra_sor_hdmi_enable()
2652 value |= SOR_PLL0_VCOCAP(settings->vcocap); in tegra_sor_hdmi_enable()
2653 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2656 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2657 value &= ~SOR_PLL1_LOADADJ_MASK; in tegra_sor_hdmi_enable()
2658 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_hdmi_enable()
2659 value |= SOR_PLL1_LOADADJ(settings->loadadj); in tegra_sor_hdmi_enable()
2660 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); in tegra_sor_hdmi_enable()
2661 value |= SOR_PLL1_TMDS_TERM; in tegra_sor_hdmi_enable()
2662 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2664 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2665 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK; in tegra_sor_hdmi_enable()
2666 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; in tegra_sor_hdmi_enable()
2667 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK; in tegra_sor_hdmi_enable()
2668 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK; in tegra_sor_hdmi_enable()
2669 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); in tegra_sor_hdmi_enable()
2670 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); in tegra_sor_hdmi_enable()
2671 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); in tegra_sor_hdmi_enable()
2672 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); in tegra_sor_hdmi_enable()
2673 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2675 value = settings->drive_current[3] << 24 | in tegra_sor_hdmi_enable()
2679 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
2681 value = settings->preemphasis[3] << 24 | in tegra_sor_hdmi_enable()
2685 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2687 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2688 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_hdmi_enable()
2689 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_hdmi_enable()
2690 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); in tegra_sor_hdmi_enable()
2691 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2693 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2694 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK; in tegra_sor_hdmi_enable()
2695 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); in tegra_sor_hdmi_enable()
2696 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2699 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2700 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
2701 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2705 value = VSYNC_H_POSITION(1); in tegra_sor_hdmi_enable()
2706 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); in tegra_sor_hdmi_enable()
2709 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2710 value &= ~DITHER_CONTROL_MASK; in tegra_sor_hdmi_enable()
2711 value &= ~BASE_COLOR_SIZE_MASK; in tegra_sor_hdmi_enable()
2715 value |= BASE_COLOR_SIZE_666; in tegra_sor_hdmi_enable()
2719 value |= BASE_COLOR_SIZE_888; in tegra_sor_hdmi_enable()
2723 value |= BASE_COLOR_SIZE_101010; in tegra_sor_hdmi_enable()
2727 value |= BASE_COLOR_SIZE_121212; in tegra_sor_hdmi_enable()
2732 value |= BASE_COLOR_SIZE_888; in tegra_sor_hdmi_enable()
2736 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2739 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2740 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_hdmi_enable()
2741 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); in tegra_sor_hdmi_enable()
2742 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2749 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2750 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; in tegra_sor_hdmi_enable()
2751 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; in tegra_sor_hdmi_enable()
2752 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2755 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2756 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; in tegra_sor_hdmi_enable()
2757 value |= SOR_HEAD_STATE_COLORSPACE_RGB; in tegra_sor_hdmi_enable()
2758 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2765 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2766 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; in tegra_sor_hdmi_enable()
2767 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2774 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2777 value |= SOR_ENABLE(1) | SOR1_TIMING_CYA; in tegra_sor_hdmi_enable()
2779 value |= SOR_ENABLE(sor->index); in tegra_sor_hdmi_enable()
2781 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2784 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2785 value &= ~PROTOCOL_MASK; in tegra_sor_hdmi_enable()
2786 value |= PROTOCOL_SINGLE_TMDS_A; in tegra_sor_hdmi_enable()
2787 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2813 u32 value; in tegra_sor_init() local
2921 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0; in tegra_sor_init()
2922 tegra_sor_writel(sor, value, SOR_INT_ENABLE); in tegra_sor_init()
2923 tegra_sor_writel(sor, value, SOR_INT_MASK); in tegra_sor_init()
3188 u32 value; in tegra_sor_parse_dt() local
3192 err = of_property_read_u32(np, "nvidia,interface", &value); in tegra_sor_parse_dt()
3196 sor->index = value; in tegra_sor_parse_dt()
3222 u32 value; in tegra_sor_irq() local
3224 value = tegra_sor_readl(sor, SOR_INT_STATUS); in tegra_sor_irq()
3225 tegra_sor_writel(sor, value, SOR_INT_STATUS); in tegra_sor_irq()
3227 if (value & SOR_INT_CODEC_SCRATCH0) { in tegra_sor_irq()
3228 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); in tegra_sor_irq()
3230 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) { in tegra_sor_irq()
3233 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; in tegra_sor_irq()