Lines Matching full:value
13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset() local
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value, in dwxgmac2_dma_reset()
19 !(value & XGMAC_SWR), 0, 100000); in dwxgmac2_dma_reset()
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init() local
28 value |= XGMAC_AAL; in dwxgmac2_dma_init()
30 writel(value | XGMAC_EAME, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
36 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan() local
39 value |= XGMAC_PBLx8; in dwxgmac2_dma_init_chan()
41 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan()
50 u32 value; in dwxgmac2_dma_init_rx_chan() local
52 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_init_rx_chan()
53 value &= ~XGMAC_RxPBL; in dwxgmac2_dma_init_rx_chan()
54 value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL; in dwxgmac2_dma_init_rx_chan()
55 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_init_rx_chan()
66 u32 value; in dwxgmac2_dma_init_tx_chan() local
68 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()
69 value &= ~XGMAC_TxPBL; in dwxgmac2_dma_init_tx_chan()
70 value |= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL; in dwxgmac2_dma_init_tx_chan()
71 value |= XGMAC_OSP; in dwxgmac2_dma_init_tx_chan()
72 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()
80 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_axi() local
84 value |= XGMAC_EN_LPI; in dwxgmac2_dma_axi()
86 value |= XGMAC_LPI_XIT_PKT; in dwxgmac2_dma_axi()
88 value &= ~XGMAC_WR_OSR_LMT; in dwxgmac2_dma_axi()
89 value |= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) & in dwxgmac2_dma_axi()
92 value &= ~XGMAC_RD_OSR_LMT; in dwxgmac2_dma_axi()
93 value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) & in dwxgmac2_dma_axi()
97 value |= XGMAC_UNDEF; in dwxgmac2_dma_axi()
99 value &= ~XGMAC_BLEN; in dwxgmac2_dma_axi()
103 value |= XGMAC_BLEN256; in dwxgmac2_dma_axi()
106 value |= XGMAC_BLEN128; in dwxgmac2_dma_axi()
109 value |= XGMAC_BLEN64; in dwxgmac2_dma_axi()
112 value |= XGMAC_BLEN32; in dwxgmac2_dma_axi()
115 value |= XGMAC_BLEN16; in dwxgmac2_dma_axi()
118 value |= XGMAC_BLEN8; in dwxgmac2_dma_axi()
121 value |= XGMAC_BLEN4; in dwxgmac2_dma_axi()
126 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_axi()
142 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); in dwxgmac2_dma_rx_mode() local
146 value |= XGMAC_RSF; in dwxgmac2_dma_rx_mode()
148 value &= ~XGMAC_RSF; in dwxgmac2_dma_rx_mode()
149 value &= ~XGMAC_RTC; in dwxgmac2_dma_rx_mode()
152 value |= 0x0 << XGMAC_RTC_SHIFT; in dwxgmac2_dma_rx_mode()
154 value |= 0x2 << XGMAC_RTC_SHIFT; in dwxgmac2_dma_rx_mode()
156 value |= 0x3 << XGMAC_RTC_SHIFT; in dwxgmac2_dma_rx_mode()
159 value &= ~XGMAC_RQS; in dwxgmac2_dma_rx_mode()
160 value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS; in dwxgmac2_dma_rx_mode()
166 value |= XGMAC_EHFC; in dwxgmac2_dma_rx_mode()
208 writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); in dwxgmac2_dma_rx_mode()
211 value = readl(ioaddr + XGMAC_MTL_QINTEN(channel)); in dwxgmac2_dma_rx_mode()
212 writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel)); in dwxgmac2_dma_rx_mode()
218 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_dma_tx_mode() local
222 value |= XGMAC_TSF; in dwxgmac2_dma_tx_mode()
224 value &= ~XGMAC_TSF; in dwxgmac2_dma_tx_mode()
225 value &= ~XGMAC_TTC; in dwxgmac2_dma_tx_mode()
228 value |= 0x0 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
230 value |= 0x2 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
232 value |= 0x3 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
234 value |= 0x4 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
236 value |= 0x5 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
238 value |= 0x6 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
240 value |= 0x7 << XGMAC_TTC_SHIFT; in dwxgmac2_dma_tx_mode()
244 value |= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP; in dwxgmac2_dma_tx_mode()
246 value &= ~XGMAC_TXQEN; in dwxgmac2_dma_tx_mode()
248 value |= 0x2 << XGMAC_TXQEN_SHIFT; in dwxgmac2_dma_tx_mode()
250 value |= 0x1 << XGMAC_TXQEN_SHIFT; in dwxgmac2_dma_tx_mode()
252 value &= ~XGMAC_TQS; in dwxgmac2_dma_tx_mode()
253 value |= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS; in dwxgmac2_dma_tx_mode()
255 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_dma_tx_mode()
270 u32 value; in dwxgmac2_dma_start_tx() local
272 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_start_tx()
273 value |= XGMAC_TXST; in dwxgmac2_dma_start_tx()
274 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_start_tx()
276 value = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_start_tx()
277 value |= XGMAC_CONFIG_TE; in dwxgmac2_dma_start_tx()
278 writel(value, ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_start_tx()
283 u32 value; in dwxgmac2_dma_stop_tx() local
285 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_stop_tx()
286 value &= ~XGMAC_TXST; in dwxgmac2_dma_stop_tx()
287 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_stop_tx()
289 value = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_stop_tx()
290 value &= ~XGMAC_CONFIG_TE; in dwxgmac2_dma_stop_tx()
291 writel(value, ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_stop_tx()
296 u32 value; in dwxgmac2_dma_start_rx() local
298 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_start_rx()
299 value |= XGMAC_RXST; in dwxgmac2_dma_start_rx()
300 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_start_rx()
302 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_dma_start_rx()
303 value |= XGMAC_CONFIG_RE; in dwxgmac2_dma_start_rx()
304 writel(value, ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_dma_start_rx()
309 u32 value; in dwxgmac2_dma_stop_rx() local
311 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_stop_rx()
312 value &= ~XGMAC_RXST; in dwxgmac2_dma_stop_rx()
313 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_stop_rx()
460 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso() local
463 value |= XGMAC_TSE; in dwxgmac2_enable_tso()
465 value &= ~XGMAC_TSE; in dwxgmac2_enable_tso()
467 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso()
472 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_qmode() local
475 value &= ~XGMAC_TXQEN; in dwxgmac2_qmode()
477 value |= 0x2 << XGMAC_TXQEN_SHIFT; in dwxgmac2_qmode()
480 value |= 0x1 << XGMAC_TXQEN_SHIFT; in dwxgmac2_qmode()
484 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_qmode()
489 u32 value; in dwxgmac2_set_bfsize() local
491 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_set_bfsize()
492 value |= bfsize << 1; in dwxgmac2_set_bfsize()
493 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_set_bfsize()
498 u32 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_enable_sph() local
500 value &= ~XGMAC_CONFIG_HDSMS; in dwxgmac2_enable_sph()
501 value |= XGMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */ in dwxgmac2_enable_sph()
502 writel(value, ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_enable_sph()
504 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_enable_sph()
506 value |= XGMAC_SPH; in dwxgmac2_enable_sph()
508 value &= ~XGMAC_SPH; in dwxgmac2_enable_sph()
509 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_enable_sph()