/Linux-v6.1/Documentation/devicetree/bindings/iio/adc/ |
D | ingenic,adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 # Copyright 2019-2020 Artur Rojek 4 --- 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#" 11 - Artur Rojek <contact@artur-rojek.eu> 17 ADC clients must use the format described in 18 https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml, 19 giving a phandle and IIO specifier pair ("io-channels") to the ADC controller. 24 - ingenic,jz4725b-adc 25 - ingenic,jz4740-adc [all …]
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/Linux-v6.1/Documentation/hwmon/ |
D | pc87360.rst | 22 ----------------- 27 - 0: None 28 - **1**: Forcibly enable internal voltage and temperature channels, 30 - 2: Forcibly enable all voltage and temperature channels, except in9 31 - 3: Forcibly enable all voltage and temperature channels, including in9 42 ----------- 56 PC87360 - 2 2 - 0xE1 57 PC87363 - 2 2 - 0xE8 58 PC87364 - 3 3 - 0xE4 60 PC87366 11 3 3 3-4 0xE9 [all …]
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D | vt1211.rst | 10 Addresses scanned: none, address read from Super-I/O config space 24 ----------------- 29 configuration for channels 1-5. 30 Legal values are in the range of 0-31. Bit 0 maps to 47 ----------- 49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring 52 implements 5 universal input channels (UCH1-5) that can be individually 60 connected to the PWM outputs of the VT1211 :-(). 66 Sensor Voltage Mode Temp Mode Default Use (from the datasheet) 69 Reading 3 temp2 Internal thermal diode [all …]
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/Linux-v6.1/drivers/hwmon/ |
D | mlxreg-fan.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 27 * FAN datasheet defines the formula for RPM calculations as RPM = 15/t-high. 28 * The logic in a programmable device measures the time t-high by sampling the 29 * tachometer every t-sample (with the default value 11.32 uS) and increment 31 * RPM = 15 / (t-sample * (K + Regval)), where: 33 * - 0xff - represents tachometer fault; 34 * - 0xfe - represents tachometer minimum value , which is 4444 RPM; 35 * - 0x00 - represents tachometer maximum value , which is 300000 RPM; 39 * used: RPM = 15 / ((Regval + K) * 11.32) * 10^(-6)), which in the 42 * - for Regval 0x00, RPM will be 15000000 * 100 / (44 * 1132) = 30115; [all …]
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/Linux-v6.1/Documentation/devicetree/bindings/timer/ |
D | nxp,sysctr-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Bai Ping <ping.bai@nxp.com> 15 etc. it is intended for use in applications where the counter 21 const: nxp,sysctr-timer 32 clock-names: 35 nxp,no-divider: 36 description: if present, means there is no internal base clk divider. [all …]
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/Linux-v6.1/drivers/gpu/drm/pl111/ |
D | pl111_drm.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 4 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. 8 * Copyright (c) 2006-2008 Intel Corporation 16 #include <linux/clk-provider.h> 27 * CLCD Controller Internal Register addresses 104 * struct pl111_variant_data - encodes IP differences 110 * @broken_clockdivider: the clock divider is broken and we need to 111 * use the supplied clock directly 144 /* The pixel clock (a reference to our clock divider off of CLCDCLK). */ 146 /* pl111's internal clock divider. */
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/Linux-v6.1/drivers/gpu/drm/amd/display/include/ |
D | bios_parser_types.h | 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 197 /* Input: Signal Type - to be converted to Encoder mode */ 207 /* Output: If non-zero, this refDiv value should be used to calculate 210 /* Output: If non-zero, this postDiv value should be used to calculate 220 /* signal_type -> Encoder Mode - needed by VBIOS Exec table */ 225 /* Calculated Reference divider of Display PLL */ 227 /* Calculated Feedback divider of Display PLL */ 229 /* Calculated Fractional Feedback divider of Display PLL */ [all …]
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/Linux-v6.1/drivers/iio/imu/inv_mpu6050/ |
D | inv_mpu_ring.c | 1 // SPDX-License-Identifier: GPL-2.0-only 19 * inv_mpu6050_update_period() - Update chip internal period estimation 33 (NSEC_PER_MSEC * (100 - INV_MPU6050_TS_PERIOD_JITTER)) / 100; in inv_mpu6050_update_period() 36 const s32 divider = INV_MPU6050_FREQ_DIVIDER(st); in inv_mpu6050_update_period() local 40 if (st->it_timestamp == 0) { in inv_mpu6050_update_period() 41 /* not initialized, forced to use it_timestamp */ in inv_mpu6050_update_period() 45 * Validate the use of it timestamp by checking if interrupt in inv_mpu6050_update_period() 51 delta = div_s64(timestamp - st->it_timestamp, divider); in inv_mpu6050_update_period() 53 /* update chip period and use it timestamp */ in inv_mpu6050_update_period() 54 st->chip_period = (st->chip_period + delta) / 2; in inv_mpu6050_update_period() [all …]
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D | inv_mpu_aux.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2019 TDK-InvenSense, Inc. 20 /* use 50hz frequency for xfer */ in inv_mpu_i2c_master_xfer() 29 ret = regmap_write(st->map, st->reg->sample_rate_div, d); in inv_mpu_i2c_master_xfer() 34 user_ctrl = st->chip_config.user_ctrl | INV_MPU6050_BIT_I2C_MST_EN; in inv_mpu_i2c_master_xfer() 35 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl); in inv_mpu_i2c_master_xfer() 39 /* wait for xfer: 1 period + half-period margin */ in inv_mpu_i2c_master_xfer() 43 user_ctrl = st->chip_config.user_ctrl; in inv_mpu_i2c_master_xfer() 44 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl); in inv_mpu_i2c_master_xfer() 49 d = st->chip_config.divider; in inv_mpu_i2c_master_xfer() [all …]
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/Linux-v6.1/arch/powerpc/platforms/512x/ |
D | clock-commonclk.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 12 #include <linux/clk-provider.h> 21 #include <dt-bindings/clock/mpc512x-clock.h> 39 /* extend the public set of clocks by adding internal slots for management */ 65 /* internal, symbolic spec for the number of slots */ 89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet 292 val &= (1 << len) - 1; in get_bit_field() 305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult() 326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2() 350 cpmf = get_bit_field(&clkregs->spmr, 16, 4); in get_cpmf_mult_x2() [all …]
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/Linux-v6.1/drivers/clk/sunxi/ |
D | clk-a20-gmac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 * Copyright 2013 Chen-Yu Tsai 7 * Chen-Yu Tsai <wens@csie.org> 10 #include <linux/clk-provider.h> 19 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module 23 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core 24 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY 25 * Ext. 125MHz RGMII TX clk >--|__divider__/ | 28 * The external 125 MHz reference is optional, i.e. GMAC can use its 29 * internal TX clock just fine. The A31 GMAC clock module does not have [all …]
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/Linux-v6.1/drivers/iio/adc/ |
D | stm32-dfsdm-core.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 20 #include "stm32-dfsdm.h" 88 unsigned int spi_clk_out_div; /* SPI clkout divider value */ 105 ret = clk_prepare_enable(priv->clk); in stm32_dfsdm_clk_prepare_enable() 106 if (ret || !priv->aclk) in stm32_dfsdm_clk_prepare_enable() 109 ret = clk_prepare_enable(priv->aclk); in stm32_dfsdm_clk_prepare_enable() 111 clk_disable_unprepare(priv->clk); in stm32_dfsdm_clk_prepare_enable() 120 clk_disable_unprepare(priv->aclk); in stm32_dfsdm_clk_disable_unprepare() 121 clk_disable_unprepare(priv->clk); in stm32_dfsdm_clk_disable_unprepare() [all …]
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/Linux-v6.1/sound/soc/fsl/ |
D | fsl_asrc.c | 1 // SPDX-License-Identifier: GPL-2.0 11 #include <linux/dma-mapping.h> 14 #include <linux/dma/imx-dma.h> 26 dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 29 dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 32 dev_warn(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 110 * According to RM, the divider range is 1 ~ 8, 114 1, 2, 4, 8, 16, 32, 64, 128, /* divider = 1 */ 115 2, 4, 8, 16, 32, 64, 128, 256, /* divider = 2 */ 116 3, 6, 12, 24, 48, 96, 192, 384, /* divider = 3 */ [all …]
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/Linux-v6.1/drivers/gpu/ipu-v3/ |
D | ipu-di.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc. 14 #include <video/imx-ipu-v3.h> 15 #include "ipu-prv.h" 76 #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1)) 77 #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1)) 78 #define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2)) 125 return readl(di->base + offset); in ipu_di_read() 130 writel(value, di->base + offset); in ipu_di_write() 166 if ((c->run_count >= 0x1000) || (c->offset_count >= 0x1000) || in ipu_di_sync_config() [all …]
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/Linux-v6.1/drivers/phy/amlogic/ |
D | phy-meson-axg-mipi-dphy.c | 1 // SPDX-License-Identifier: GPL-2.0 33 * [11] mipi divider clk selection. 34 * 1: select the mipi DDRCLKHS from clock divider. 36 * [10] mipi clock divider control. 38 * [9] mipi divider output enable. 39 * [8] mipi divider counter enable. 46 * [1] write 1 to sync the txclkesc input. the internal logic have to 47 * use txclkesc to decide Txvalid and Txready. 53 * 1: from register. 0: use clk lane state machine. 188 ret = phy_init(priv->analog); in phy_meson_axg_mipi_dphy_init() [all …]
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/Linux-v6.1/drivers/clk/davinci/ |
D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0 7 * Based on arch/arm/mach-davinci/clock.c 8 * Copyright (C) 2006-2007 Texas Instruments. 9 * Copyright (C) 2008-2009 Deep Root Systems, LLC 12 #include <linux/clk-provider.h> 24 #include <linux/platform_data/clk-davinci-pll.h> 80 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN 87 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */ 91 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4 97 * struct davinci_pll_clk - Main PLL clock (aka PLLOUT) [all …]
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/Linux-v6.1/Documentation/devicetree/bindings/clock/ |
D | silabs,si5341.txt | 6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf 8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf 10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf 14 in turn can be directed to any of the 10 (or 4) outputs through a divider. 15 The internal structure of the clock generators can be found in [2]. 21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not 33 - compatible: shall be one of the following: 34 "silabs,si5340" - Si5340 A/B/C/D 35 "silabs,si5341" - Si5341 A/B/C/D 36 "silabs,si5342" - Si5342 A/B/C/D [all …]
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D | stericsson,u8500-clks.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ST-Ericsson DB8500 (U8500) clocks 10 - Ulf Hansson <ulf.hansson@linaro.org> 11 - Linus Walleij <linus.walleij@linaro.org> 14 DB8500 digital baseband system-on-chip and its siblings such as 16 itself, not off-chip clocks. There are four different on-chip 17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and [all …]
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/Linux-v6.1/drivers/gpu/drm/radeon/ |
D | radeon_display.c | 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 52 struct drm_device *dev = crtc->dev; in avivo_crtc_load_lut() 53 struct radeon_device *rdev = dev->dev_private; in avivo_crtc_load_lut() 57 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in avivo_crtc_load_lut() 58 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut() 60 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut() 61 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut() 62 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut() [all …]
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/Linux-v6.1/include/linux/ |
D | clk-provider.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> 4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> 14 * top-level framework. custom flags for dealing with hardware specifics 20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 31 /* parents need enable during gate/ungate, set rate and re-parent */ 42 * struct clk_rate_request - Structure encoding the clk constraints that [all …]
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/Linux-v6.1/drivers/spi/ |
D | spi-orion.c | 1 // SPDX-License-Identifier: GPL-2.0-only 6 * Copyright (C) 2007-2008 Marvell Ltd. 30 * It is up to the implementer to only use the chip selects 74 * have both is for managing the armada-370-spi case with old 111 return orion_spi->base + reg; in spi_reg() 145 orion_spi = spi_master_get_devdata(spi->master); in orion_spi_baudrate_set() 146 devdata = orion_spi->devdata; in orion_spi_baudrate_set() 148 tclk_hz = clk_get_rate(orion_spi->clk); in orion_spi_baudrate_set() 150 if (devdata->typ == ARMADA_SPI) { in orion_spi_baudrate_set() 161 /* best integer divider: */ in orion_spi_baudrate_set() [all …]
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/Linux-v6.1/drivers/comedi/drivers/ |
D | dt2811.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * COMEDI - Linux Control and Measurement Device Interface 13 * Devices: [Data Translation] DT2811-PGL (dt2811-pgl), DT2811-PGH (dt2811-pgh) 17 * [0] - I/O port base address 18 * [1] - IRQ (optional, needed for async command support) 19 * [2] - A/D reference (# of analog inputs) 20 * 0 = single-ended (16 channels) 22 * 2 = pseudo-differential (16 channels) 23 * [3] - A/D range (deprecated, see below) 24 * [4] - D/A 0 range (deprecated, see below) [all …]
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/Linux-v6.1/sound/soc/ti/ |
D | omap-mcbsp.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port 24 #include "omap-mcbsp-priv.h" 25 #include "omap-mcbsp.h" 26 #include "sdma-pcm.h" 41 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id); in omap_mcbsp_dump_reg() 42 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2)); in omap_mcbsp_dump_reg() 43 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1)); in omap_mcbsp_dump_reg() 44 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2)); in omap_mcbsp_dump_reg() 45 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1)); in omap_mcbsp_dump_reg() [all …]
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/Linux-v6.1/drivers/clocksource/ |
D | timer-microchip-pit64b.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * 64-bit Periodic Interval Timer driver 50 * struct mchp_pit64b_timer - PIT64B timer data structure 64 * struct mchp_pit64b_clkevt - PIT64B clockevent data structure 78 * struct mchp_pit64b_clksrc - PIT64B clocksource data structure 124 writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); in mchp_pit64b_reset() 125 writel_relaxed(mode | timer->mode, timer->base + MCHP_PIT64B_MR); in mchp_pit64b_reset() 126 writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR); in mchp_pit64b_reset() 127 writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR); in mchp_pit64b_reset() 128 writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER); in mchp_pit64b_reset() [all …]
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/Linux-v6.1/drivers/gpu/drm/amd/include/ |
D | atombios.h | 2 * Copyright 2006-2007 Advanced Micro Devices, Inc. 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication 108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication 110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,… 191 #pragma pack(1) // BIOS data must use byte alignment 222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, 245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, 300 … //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead [all …]
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