Lines Matching +full:use +full:- +full:internal +full:- +full:divider
2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
191 #pragma pack(1) // BIOS data must use byte alignment
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
300 … //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
343 … //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssi…
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
460 …icable to memory clock change, when set, the table will skip predefined internal memory parameter …
467 …icable to memory clock change, when set, the table will skip predefined internal memory parameter …
471 #define b3SRIOV_INIT_BOOT 0x40 //Use by HV GPU driver only, to load u…
472 #define b3SRIOV_LOAD_UCODE 0x40 //Use by HV GPU driver only, to load u…
473 #define b3SRIOV_SKIP_ASIC_INIT 0x02 //Use by HV GPU driver only, skip ASIC…
517 …ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register d…
521 …ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register d…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
558 …COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider
559 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider
560 UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider
561 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider
582 …COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider
583 USHORT usSclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536
584 USHORT usSclk_fcw_int; //integer divider of fcwc
585 UCHAR ucSclkPostDiv; //PLL post divider = 2^ucSclkPostDiv
598 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
600 // use for ComputeMemoryClockParamTable
606 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
611 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
628 // use for ComputeMemoryClockParamTable
638 USHORT usMclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536
639 USHORT usMclk_fcw_int; //integer divider of fcwc
813 … // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate …
866 #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside S…
949 #define ATOM_ENCODER_CMD_LINK_SETUP 0x11 //internal use, called by other Com…
950 #define ATOM_ENCODER_CMD_ENCODER_BLANK 0x12 //internal use, called by other Com…
958 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
1000 // =0x1: internal DP2
1001 // =0x11: internal DP1 for NutMeg/Travis DP translator
1011 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
1059 // =0x1: internal DP2
1060 // =0x11: internal DP1 for NutMeg/Travis DP translator
1064 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
1101 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1110 // =0x1: internal DP2
1111 // =0x11: internal DP1 NutMeg/Travis DP Translator
1380 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1384 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1482 UCHAR ucLaneNum; // indicate lane number 1-8
1566 …UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP…
1571 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1821 USHORT usRefDiv; // Reference divider
1822 USHORT usFbDiv; // feedback divider
1823 UCHAR ucPostDiv; // post divider
1824 UCHAR ucFracFbDiv; // fractional feedback divider
1841 USHORT usRefDiv; // Reference divider
1842 USHORT usFbDiv; // feedback divider
1843 UCHAR ucPostDiv; // post divider
1844 UCHAR ucFracFbDiv; // fractional feedback divider
1888 USHORT usRefDiv; // Reference divider
1889 USHORT usFbDiv; // feedback divider
1890 UCHAR ucPostDiv; // post divider
1891 UCHAR ucFracFbDiv; // fractional feedback divider
1897 …UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
1900 … // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1901 …// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the sour…
1918 USHORT usFbDiv; // feedback divider integer part.
1919 UCHAR ucPostDiv; // post divider.
1920 UCHAR ucRefDiv; // Reference divider
1930 // =1: other external clock source, which is pre-defined
1933 …ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 (…
1966 USHORT usFbDiv; // feedback divider integer part.
1967 UCHAR ucPostDiv; // post divider.
1968 UCHAR ucRefDiv; // Reference divider
1978 // =1: other external clock source, which is pre-defined
1981 …ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 (…
2046 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: D…
2047 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO:…
2048 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO:…
2049 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO:…
2056 UCHAR ucCrtc; // use when enable DCCG pixel clock ucFlag[1]=1
2057 UCHAR ucPpllId; // use when enable DCCG pixel clock ucFlag[1]=1
2058 UCHAR ucDeepColorRatio; // use when enable DCCG pixel clock ucFlag[1]=1
2080 …UCHAR ucCRTC; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only…
2097 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE:…
2098 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATI…
2099 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATI…
2100 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATI…
2156 …UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other …
2157 …UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other …
2203 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
2208 …USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware stat…
2209 … //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
2296 …cture is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
2311 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2312 // Bit[1]: 1-Ext. 0-Int.
2336 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2337 // Bit[1]: 1-Ext. 0-Int.
2532 // bit1=0: non-coherent mode
2607 …UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power …
2792 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1
2816 …_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2962 UCHAR ucPadding[3]; //Don't use them
2963 ULONG aulReservedForBIOS[3]; //Don't use them
2997 UCHAR ucPadding[2]; //Don't use them
2998 ULONG aulReservedForBIOS[2]; //Don't use them
3009 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3033 UCHAR ucPadding[2]; //Don't use them
3034 ULONG aulReservedForBIOS; //Don't use them
3046 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3084 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3123 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3127 …Freq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise I…
3175 …Freq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise I…
3234 … For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
3266 …s to never change table revisions. Whenever needed, a GPU SW component can use reserved portion fo…
3310 … // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
3315 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
3316 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
3317 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
3320 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
3321 … or user customized mode. In this case, driver will just stick to this boot-up mode. No other Pow…
3339 …ord is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEV…
3341 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
3342 …[7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are suppor…
3345 …[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lan…
3346 …[7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station…
3349 …one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connect…
3351 [15:8] - Lane configuration attribute;
3352 [23:16]- Connector type, possible value:
3358 [31:24]- Reserved
3366 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offs…
3380 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
3409 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
3517 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
3630 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3631 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3632 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3633 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3634 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3635 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3636 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3637 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3638 // Bit 8 = 0 - no CV support= 1- CV is supported
3639 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3640 // Bit 10= 0 - no DFP4 support= 1- DFP4 is supported
3641 // Bit 11= 0 - no DFP5 support= 1- DFP5 is supported
3649 // [7:0] - I2C LINE Associate ID
3650 // = 0 - no I2C
3651 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3653 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3654 // = 2, HW engine for Multimedia use
3655 // = 3-7 Reserved for future I2C engines
3656 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3761 // usModeMiscInfo-
3773 //usRefreshRate-
3785 // Translation from EDID to ATOM_MODE_TIMING, use the following formula.
3947 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set…
3952 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3958 // 0 0 0 - Color bit depth is undefined
3959 // 0 0 1 - 6 Bits per Primary Color
3960 // 0 1 0 - 8 Bits per Primary Color
3961 // 0 1 1 - 10 Bits per Primary Color
3962 // 1 0 0 - 12 Bits per Primary Color
3963 // 1 0 1 - 14 Bits per Primary Color
3964 // 1 1 0 - 16 Bits per Primary Color
3965 // 1 1 1 - Reserved
4014 // Bit7-3: Reserved
4052 // 0 0 0 - Color bit depth is undefined
4053 // 0 0 1 - 6 Bits per Primary Color
4054 // 0 1 0 - 8 Bits per Primary Color
4055 // 0 1 1 - 10 Bits per Primary Color
4056 // 1 0 0 - 12 Bits per Primary Color
4057 // 1 0 1 - 14 Bits per Primary Color
4058 // 1 1 0 - 16 Bits per Primary Color
4059 // 1 1 1 - Reserved
4067 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set…
4072 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
4076 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
4077 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip with…
4093 //!! If the record below exits, it shoud always be the first record for easy use in command table!!!
4094 // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel…
4144 …0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_Info…
4145 #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP s…
4222 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
4236 … (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
4294 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)…
4310 // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware
4318 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
4322 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
4324 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
4368 //ucGPIO_ID pre-define id for multiple usage
4369 // GPIO use to control PCIE_VDDC in certain SLT board
4380 // ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; u…
4382 // Thermal interrupt output->system thermal chip GPIO pin
4459 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4476 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4525 …USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encode…
4650 #define EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 (0x03 << 2 ) //Parade DP->HDMI recov…
4661 UCHAR uc3DStereoPinId; // use for eDP panel
4680 #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD…
4681 #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD…
4683 #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD…
4788 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4844 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4850 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4864 …USHORT usReserved:12; // Bit4-15 may be defined for other capability in fu…
4874 …USHORT usReserved:12; // Bit4-15 may be defined for other capability in fu…
4932 …HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO tab…
4938 …MBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID
5019 …UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - Ba…
5117 #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_V…
5118 …I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OB…
5119 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GP…
5120 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SV…
5122 …OST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5123 …AKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5124 …AKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5147 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data
5181 // 14:7 - PSI0_VID
5182 // 6 - PSI0_EN
5183 // 5 - PSI1
5184 // 4:2 - load line slope trim.
5185 // 1:0 - offset trim,
5272 //Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2
5276 … // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5278 …ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative n…
5282 //Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min )
5286 … // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5288 …ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative n…
5626 UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz
5809 …tup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup eng…
5825 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
5826 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
5834 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5835 …WM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should…
5837 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5840 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5843 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5854 Bit[1]=0: DDR-DLL shut-down feature disabled.
5855 1: DDR-DLL shut-down feature enabled.
5856 Bit[2]=0: DDR-PLL Power down feature disabled.
5857 1: DDR-PLL Power down feature enabled.
5876 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
5877 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5882 …panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setti…
5883 …S panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setti…
5884 … HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setti…
5885 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS de…
5886 … DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setti…
5887 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS def…
5888 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use defa…
6029 …tup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup eng…
6051 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
6052 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
6053 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
6054 =1: DP mode use single PLL mode
6063 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
6064 …WM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should…
6066 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
6069 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
6072 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
6083 Bit[1]=0: DDR-DLL shut-down feature disabled.
6084 1: DDR-DLL shut-down feature enabled.
6085 Bit[2]=0: DDR-PLL Power down feature disabled.
6086 1: DDR-PLL Power down feature enabled.
6107 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
6108 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
6113 …panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setti…
6114 …S panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setti…
6115 … HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setti…
6116 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS de…
6117 … DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setti…
6118 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS def…
6119 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use defa…
6125 …[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to ove…
6126 … means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdju…
6129 …=0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->…
6132 …=0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON…
6136 …=0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following:…
6140 …=0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLO…
6144 =0 means to use VBIOS default delay which is 125 ( 500ms ).
6149 =0 means to use VBIOS default delay which is 0 ( 0ms ).
6154 =0 means to use VBIOS default delay which is 0 ( 0ms ).
6231 …tup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup eng…
6265 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
6266 …WM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should…
6268 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
6271 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
6274 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
6284 Bit[1]=0: DDR-DLL shut-down feature disabled.
6285 1: DDR-DLL shut-down feature enabled.
6286 Bit[2]=0: DDR-PLL Power down feature disabled.
6287 1: DDR-PLL Power down feature enabled.
6308 … NCLK speed while memory runs in self-refresh state, used to calculate self-re…
6314 …panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setti…
6315 …S panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setti…
6316 … HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setti…
6317 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS de…
6318 … DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setti…
6319 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS def…
6325 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use defa…
6331 …[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to ove…
6332 … means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdju…
6336 …=0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->…
6340 …=0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON…
6344 …=0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following:…
6348 …=0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLO…
6352 =0 means to use VBIOS default delay which is 125 ( 500ms ).
6356 =0 means to use VBIOS default delay which is 0 ( 0ms ).
6361 =0 means to use VBIOS default delay which is 0 ( 0ms ).
6367 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
6368 ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State
6369 usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
6370 usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded
6661 …ctrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: extern…
6692 …ctrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: extern…
6845 #define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode…
7146 …char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<cha…
7148 …ADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevisio…
7149 …DER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevisi…
7153 …SION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevisio…
7154 …ION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevisi…
7281 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
7288 … USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
7391 UCHAR ucTV_Mode_Num; //Internal TV mode number
7397 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table
7577 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
7615 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7616 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7633 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
7642 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7643 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7651 …// memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
7687 …// memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
7723 …// memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
7769 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
7794 … ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
7811 …USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, u…
7815 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7817 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7820 …; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
7824 …UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, u…
7825 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7853 …USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, u…
7857 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7859 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7862 …; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
7866 …UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, u…
7867 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7876 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7885 …USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, u…
7889 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7891 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7894 …; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
7898 …UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, u…
7899 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7908 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7924 …UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memo…
7927 … // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
7929 …Size; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7938 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7968 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
8006 … ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bi…
8039 …Num; // indicate the MCD tile number which use in DramDataRemapTbl…
8229 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
8230 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
8444 UCHAR ucI2cId; // use for GET_SINK_TYPE command
8460 …USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucActio…
8573 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8574 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
8575 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
8582 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8583 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
8584 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
8594 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8595 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
8596 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
8601 …fset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Lin…
8602 …t of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Lin…
8603 … of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Lin…
8604 …set of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Lin…
8605 …f PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Lin…
8606 …TING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Lin…
8773 // [7:4] - connector type
8774 // = 1 - VGA connector
8775 // = 2 - DVI-I
8776 // = 3 - DVI-D
8777 // = 4 - DVI-A
8778 // = 5 - SVIDEO
8779 // = 6 - COMPOSITE
8780 // = 7 - LVDS
8781 // = 8 - DIGITAL LINK
8782 // = 9 - SCART
8783 // = 0xA - HDMI_type A
8784 // = 0xB - HDMI_type B
8785 // = 0xE - Special case1 (DVI+DIN)
8787 // [3:0] - DAC Associated
8788 // = 0 - no DAC
8789 // = 1 - DACA
8790 // = 2 - DACB
8791 // = 3 - External DAC
8856 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
8896 …UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate d…
8966 …SCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-…
8976 …ETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-Hi…
8986 …O2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver …
8987 …//If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video pla…
9209 #pragma pack() // BIOS data must use byte alignment
9223 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production )
9240 #pragma pack() // BIOS data must use byte alignment