1 // SPDX-License-Identifier: GPL-2.0
3  * 64-bit Periodic Interval Timer driver
50  * struct mchp_pit64b_timer - PIT64B timer data structure
64  * struct mchp_pit64b_clkevt - PIT64B clockevent data structure
78  * struct mchp_pit64b_clksrc - PIT64B clocksource data structure
124 	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);  in mchp_pit64b_reset()
125 	writel_relaxed(mode | timer->mode, timer->base + MCHP_PIT64B_MR);  in mchp_pit64b_reset()
126 	writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR);  in mchp_pit64b_reset()
127 	writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR);  in mchp_pit64b_reset()
128 	writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER);  in mchp_pit64b_reset()
129 	writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);  in mchp_pit64b_reset()
134 	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);  in mchp_pit64b_suspend()
135 	if (timer->mode & MCHP_PIT64B_MR_SGCLK)  in mchp_pit64b_suspend()
136 		clk_disable_unprepare(timer->gclk);  in mchp_pit64b_suspend()
137 	clk_disable_unprepare(timer->pclk);  in mchp_pit64b_suspend()
142 	clk_prepare_enable(timer->pclk);  in mchp_pit64b_resume()
143 	if (timer->mode & MCHP_PIT64B_MR_SGCLK)  in mchp_pit64b_resume()
144 		clk_prepare_enable(timer->gclk);  in mchp_pit64b_resume()
224 	readl_relaxed(irq_data->timer.base + MCHP_PIT64B_ISR);  in mchp_pit64b_interrupt()
226 	irq_data->clkevt.event_handler(&irq_data->clkevt);  in mchp_pit64b_interrupt()
242 	/* Use the biggest prescaler if we didn't match one. */  in mchp_pit64b_pres_compute()
244 		*pres = MCHP_PIT64B_PRES_MAX - 1;  in mchp_pit64b_pres_compute()
248  * mchp_pit64b_init_mode() - prepare PIT64B mode register value to be used at
251  * @max_rate: maximum rate that timer's clock could use
256  * divided by the internal PIT64B's divider.
258  * This function, first tries to use GCLK by requesting the desired rate from
259  * PMC and then using the internal PIT64B prescaler, if any, to reach the
268  *  PMC             +------------------------------------+
269  * +----+           |   +-----+                          |
270  * |    |-->gclk -->|-->|     |    +---------+  +-----+  |
271  * |    |           |   | MUX |--->| Divider |->|timer|  |
272  * |    |-->pclk -->|-->|     |    +---------+  +-----+  |
273  * +----+           |   +-----+                          |
276  *                  +------------------------------------+
279  *	- gclk rate <= pclk rate/3
280  *	- gclk rate could be requested from PMC
281  *	- pclk rate is fixed (cannot be requested from PMC)
290 	pclk_rate = clk_get_rate(timer->pclk);  in mchp_pit64b_init_mode()
292 		return -EINVAL;  in mchp_pit64b_init_mode()
294 	timer->mode = 0;  in mchp_pit64b_init_mode()
297 	gclk_round = clk_round_rate(timer->gclk, max_rate);  in mchp_pit64b_init_mode()
305 	best_diff = abs(gclk_round / (pres + 1) - max_rate);  in mchp_pit64b_init_mode()
309 		timer->mode |= MCHP_PIT64B_MR_SGCLK;  in mchp_pit64b_init_mode()
310 		clk_set_rate(timer->gclk, gclk_round);  in mchp_pit64b_init_mode()
317 	diff = abs(pclk_rate / (pres + 1) - max_rate);  in mchp_pit64b_init_mode()
320 		/* Use PCLK. */  in mchp_pit64b_init_mode()
323 		/* Use GCLK. */  in mchp_pit64b_init_mode()
324 		timer->mode |= MCHP_PIT64B_MR_SGCLK;  in mchp_pit64b_init_mode()
325 		clk_set_rate(timer->gclk, gclk_round);  in mchp_pit64b_init_mode()
329 	timer->mode |= MCHP_PIT64B_PRES_TO_MODE(best_pres);  in mchp_pit64b_init_mode()
332 		timer->mode & MCHP_PIT64B_MR_SGCLK ? "gclk" : "pclk", best_pres,  in mchp_pit64b_init_mode()
333 		timer->mode & MCHP_PIT64B_MR_SGCLK ?  in mchp_pit64b_init_mode()
347 		return -ENOMEM;  in mchp_pit64b_init_clksrc()
352 	mchp_pit64b_cs_base = timer->base;  in mchp_pit64b_init_clksrc()
354 	cs->timer.base = timer->base;  in mchp_pit64b_init_clksrc()
355 	cs->timer.pclk = timer->pclk;  in mchp_pit64b_init_clksrc()
356 	cs->timer.gclk = timer->gclk;  in mchp_pit64b_init_clksrc()
357 	cs->timer.mode = timer->mode;  in mchp_pit64b_init_clksrc()
358 	cs->clksrc.name = MCHP_PIT64B_NAME;  in mchp_pit64b_init_clksrc()
359 	cs->clksrc.mask = CLOCKSOURCE_MASK(64);  in mchp_pit64b_init_clksrc()
360 	cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;  in mchp_pit64b_init_clksrc()
361 	cs->clksrc.rating = 210;  in mchp_pit64b_init_clksrc()
362 	cs->clksrc.read = mchp_pit64b_clksrc_read;  in mchp_pit64b_init_clksrc()
363 	cs->clksrc.suspend = mchp_pit64b_clksrc_suspend;  in mchp_pit64b_init_clksrc()
364 	cs->clksrc.resume = mchp_pit64b_clksrc_resume;  in mchp_pit64b_init_clksrc()
366 	ret = clocksource_register_hz(&cs->clksrc, clk_rate);  in mchp_pit64b_init_clksrc()
390 		return -ENOMEM;  in mchp_pit64b_init_clkevt()
394 	ce->timer.base = timer->base;  in mchp_pit64b_init_clkevt()
395 	ce->timer.pclk = timer->pclk;  in mchp_pit64b_init_clkevt()
396 	ce->timer.gclk = timer->gclk;  in mchp_pit64b_init_clkevt()
397 	ce->timer.mode = timer->mode;  in mchp_pit64b_init_clkevt()
398 	ce->clkevt.name = MCHP_PIT64B_NAME;  in mchp_pit64b_init_clkevt()
399 	ce->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;  in mchp_pit64b_init_clkevt()
400 	ce->clkevt.rating = 150;  in mchp_pit64b_init_clkevt()
401 	ce->clkevt.set_state_shutdown = mchp_pit64b_clkevt_shutdown;  in mchp_pit64b_init_clkevt()
402 	ce->clkevt.set_state_periodic = mchp_pit64b_clkevt_set_periodic;  in mchp_pit64b_init_clkevt()
403 	ce->clkevt.set_state_oneshot = mchp_pit64b_clkevt_set_oneshot;  in mchp_pit64b_init_clkevt()
404 	ce->clkevt.set_next_event = mchp_pit64b_clkevt_set_next_event;  in mchp_pit64b_init_clkevt()
405 	ce->clkevt.cpumask = cpumask_of(0);  in mchp_pit64b_init_clkevt()
406 	ce->clkevt.irq = irq;  in mchp_pit64b_init_clkevt()
416 	clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX);  in mchp_pit64b_init_clkevt()
440 		return -ENXIO;  in mchp_pit64b_dt_init_timer()
445 			ret = -ENODEV;  in mchp_pit64b_dt_init_timer()
493 	return -EINVAL;  in mchp_pit64b_dt_init()
496 TIMER_OF_DECLARE(mchp_pit64b, "microchip,sam9x60-pit64b", mchp_pit64b_dt_init);