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/Linux-v5.15/arch/arm/boot/dts/
Dstm32h743.dtsi45 #include <dt-bindings/mfd/stm32h7-rcc.h>
77 clocks = <&rcc TIM5_CK>;
85 clocks = <&rcc LPTIM1_CK>;
113 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
114 clocks = <&rcc SPI2_CK>;
125 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
126 clocks = <&rcc SPI3_CK>;
135 clocks = <&rcc USART2_CK>;
143 clocks = <&rcc USART3_CK>;
151 clocks = <&rcc UART4_CK>;
[all …]
Dstm32f429.dtsi50 #include <dt-bindings/mfd/stm32f4-rcc.h>
100 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
130 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
160 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
169 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
190 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
198 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
[all …]
Dstm32f746.dtsi45 #include <dt-bindings/mfd/stm32f7-rcc.h>
82 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
91 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
112 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
121 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
142 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
151 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
172 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
180 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
201 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
[all …]
Dstm32mp151.dtsi130 clocks = <&rcc TIM2_K>;
163 clocks = <&rcc TIM3_K>;
197 clocks = <&rcc TIM4_K>;
229 clocks = <&rcc TIM5_K>;
263 clocks = <&rcc TIM6_K>;
281 clocks = <&rcc TIM7_K>;
299 clocks = <&rcc TIM12_K>;
321 clocks = <&rcc TIM13_K>;
343 clocks = <&rcc TIM14_K>;
366 clocks = <&rcc LPTIM1_K>;
[all …]
Dstm32mp157.dtsi15 clocks = <&rcc GPU>, <&rcc GPU_K>;
17 resets = <&rcc GPU_R>;
23 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
25 resets = <&rcc DSI_R>;
Dstm32f7-pinctrl.dtsi8 #include <dt-bindings/mfd/stm32f7-rcc.h>
26 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
36 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
46 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
56 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
66 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
76 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
86 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
96 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
106 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
[all …]
Dstm32mp153.dtsi33 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
46 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
Dstm32f769-disco.dts91 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
103 &rcc {
104 compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc";
Dstm32f4-pinctrl.dtsi44 #include <dt-bindings/mfd/stm32f4-rcc.h>
62 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
72 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
82 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
92 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
102 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
112 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
122 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
132 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
142 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
[all …]
Dstm32mp157c-odyssey.dts33 assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>;
34 assigned-clock-parents = <&rcc PLL4_P>;
Dstm32f469.dtsi11 resets = <&rcc STM32F4_APB2_RESET(DSI)>;
13 clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
Dstm32mp15xc.dtsi13 clocks = <&rcc CRYP1>;
14 resets = <&rcc CRYP1_R>;
/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
29 rcc: rcc@40023800 {
32 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
42 The secondary index is the bit number within the RCC register bank, starting
43 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
49 drivers of the RCC IP, macros are available to generate the index in
[all …]
Dst,stm32mp1-rcc.yaml4 $id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml#
13 The RCC IP is both a reset and a clock controller.
14 RCC makes also power management (resume/supend and wakeup interrupt).
33 The index is the bit number within the RCC registers bank, starting from RCC
58 - st,stm32mp1-rcc-secure
59 - st,stm32mp1-rcc
75 rcc: rcc@50000000 {
76 compatible = "st,stm32mp1-rcc-secure", "syscon";
Dst,stm32h7-rcc.txt4 The RCC IP is both a reset and a clock controller.
11 "st,stm32h743-rcc"
31 rcc: reset-clock-controller@58024400 {
32 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
50 clocks = <&rcc TIM5_CK>;
59 The index is the bit number within the RCC registers bank, starting from RCC
70 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
/Linux-v5.15/Documentation/devicetree/bindings/net/
Dstm32-dwmac.yaml77 set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
83 select RCC clock instead of ETH_REF_CLK.
99 #include <dt-bindings/mfd/stm32h7-rcc.h>
112 clocks = <&rcc ETHMAC>,
113 <&rcc ETHTX>,
114 <&rcc ETHRX>,
115 <&rcc ETHSTP>,
116 <&rcc ETHCK_K>;
132 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
147 clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
/Linux-v5.15/drivers/clk/qcom/
Dclk-rpm.c250 struct rpm_cc *rcc = r->rpm_cc; in clk_rpm_xo_prepare() local
254 mutex_lock(&rcc->xo_lock); in clk_rpm_xo_prepare()
256 value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset); in clk_rpm_xo_prepare()
260 rcc->xo_buffer_value = value; in clk_rpm_xo_prepare()
263 mutex_unlock(&rcc->xo_lock); in clk_rpm_xo_prepare()
271 struct rpm_cc *rcc = r->rpm_cc; in clk_rpm_xo_unprepare() local
275 mutex_lock(&rcc->xo_lock); in clk_rpm_xo_unprepare()
277 value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset); in clk_rpm_xo_unprepare()
281 rcc->xo_buffer_value = value; in clk_rpm_xo_unprepare()
284 mutex_unlock(&rcc->xo_lock); in clk_rpm_xo_unprepare()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/i2c/
Dst,stm32-i2c.yaml101 #include <dt-bindings/mfd/stm32f7-rcc.h>
111 resets = <&rcc 277>;
112 clocks = <&rcc 0 149>;
123 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
124 clocks = <&rcc 1 CLK_I2C1>;
138 clocks = <&rcc I2C2_K>;
139 resets = <&rcc I2C2_R>;
/Linux-v5.15/Documentation/devicetree/bindings/rtc/
Dst,stm32-rtc.yaml117 #include <dt-bindings/mfd/stm32f4-rcc.h>
122 clocks = <&rcc 1 CLK_RTC>;
123 assigned-clocks = <&rcc 1 CLK_RTC>;
124 assigned-clock-parents = <&rcc 1 CLK_LSE>;
135 clocks = <&rcc RTCAPB>, <&rcc RTC>;
/Linux-v5.15/Documentation/devicetree/bindings/sound/
Dst,stm32-i2s.yaml81 clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
Dst,stm32-sai.yaml178 clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
190 clocks = <&rcc SAI2_K>;
/Linux-v5.15/Documentation/devicetree/bindings/remoteproc/
Dst,stm32-rproc.yaml40 Reference to the system configuration which holds the RCC trust zone mode
134 resets = <&rcc MCU_R>;
135 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
136 st,syscfg-tz = <&rcc 0x000 0x1>;
/Linux-v5.15/Documentation/devicetree/bindings/reset/
Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
6 Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
Dst,stm32mp1-rcc.txt4 The RCC IP is both a reset and a clock controller.
6 Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
/Linux-v5.15/Documentation/devicetree/bindings/display/
Dst,stm32-dsi.yaml85 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
87 resets = <&rcc DSI_R>;

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