Lines Matching full:rcc
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
100 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
130 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
160 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
169 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
190 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
198 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
228 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
243 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
252 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
268 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
288 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
302 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
316 clocks = <&rcc 1 CLK_RTC>;
317 assigned-clocks = <&rcc 1 CLK_RTC>;
318 assigned-clock-parents = <&rcc 1 CLK_LSE>;
339 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
349 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
357 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
365 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
376 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
384 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
393 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
394 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
405 resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
406 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
415 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
416 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
441 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
449 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
458 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
480 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
501 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
512 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
520 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
532 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
544 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
556 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
569 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
582 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
592 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
614 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
634 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
648 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
665 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
678 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
691 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
692 clocks = <&rcc 1 CLK_LCD>;
700 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
704 rcc: rcc@40023800 { label
707 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
711 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
726 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
741 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
753 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
754 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
755 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
766 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
775 clocks = <&rcc 0 39>;
784 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
785 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
797 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
804 clocks = <&rcc 1 SYSTICK>;