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/Linux-v6.1/Documentation/devicetree/bindings/pci/
Dbrcm,iproc-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom iProc PCIe controller with the platform bus interface
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-bus.yaml#
15 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
20 - enum:
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Dsocionext,uniphier-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
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Dsnps,dw-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe endpoint interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller endpoint
17 - $ref: /schemas/pci/pci-ep.yaml#
22 - {}
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Dti-pci.txt3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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/Linux-v6.1/drivers/pci/controller/
Dpcie-iproc-platform.c1 // SPDX-License-Identifier: GPL-2.0
20 #include "pcie-iproc.h"
24 .compatible = "brcm,iproc-pcie",
27 .compatible = "brcm,iproc-pcie-paxb-v2",
30 .compatible = "brcm,iproc-pcie-paxc",
33 .compatible = "brcm,iproc-pcie-paxc-v2",
42 struct device *dev = &pdev->dev; in iproc_pltfm_pcie_probe()
43 struct iproc_pcie *pcie; in iproc_pltfm_pcie_probe() local
44 struct device_node *np = dev->of_node; in iproc_pltfm_pcie_probe()
49 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in iproc_pltfm_pcie_probe()
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Dpcie-iproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
25 #include "pcie-iproc.h"
92 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
139 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
151 * struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
160 * @imap_addr_offset: register offset between the upper and lower 32-bit
230 * iProc PCIe host registers
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Dpcie-iproc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2014-2015 Broadcom Corporation
10 * enum iproc_pcie_type - iProc PCIe interface type
11 * @IPROC_PCIE_PAXB_BCMA: BCMA-based host controllers
12 * @IPROC_PCIE_PAXB: PAXB-based host controllers for
14 * @IPROC_PCIE_PAXB_V2: PAXB-based host controllers for Stingray SoCs
15 * @IPROC_PCIE_PAXC: PAXC-based host controllers
16 * @IPROC_PCIE_PAXC_V2: PAXC-based host controllers (second generation)
33 * struct iproc_pcie_ob - iProc PCIe outbound mapping
35 * the iProc PCIe core
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/Linux-v6.1/arch/arm64/boot/dts/broadcom/northstar2/
Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
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/Linux-v6.1/drivers/pci/controller/dwc/
Dpcie-designware.c1 // SPDX-License-Identifier: GPL-2.0
3 * Synopsys DesignWare PCIe host controller driver
20 #include "pcie-designware.h"
26 /* The content of the CSR is zero on DWC PCIe older than v4.70a */ in dw_pcie_version_detect()
31 if (pci->version && pci->version != ver) in dw_pcie_version_detect()
32 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n", in dw_pcie_version_detect()
33 pci->version, ver); in dw_pcie_version_detect()
35 pci->version = ver; in dw_pcie_version_detect()
39 if (pci->type && pci->type != ver) in dw_pcie_version_detect()
40 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n", in dw_pcie_version_detect()
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/Linux-v6.1/arch/arm64/boot/dts/rockchip/
Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
16 clock-names = "sata", "pmalive", "rxoob";
19 phy-names = "sata-phy";
20 ports-implemented = <0x1>;
21 power-domains = <&power RK3568_PD_PIPE>;
26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
31 compatible = "rockchip,rk3568-qos", "syscon";
36 compatible = "rockchip,rk3568-qos", "syscon";
41 compatible = "rockchip,rk3568-qos", "syscon";
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Drk356x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
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/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
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Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
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Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
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/Linux-v6.1/drivers/pci/endpoint/functions/
Dpci-epf-ntb.c1 // SPDX-License-Identifier: GPL-2.0
3 * Endpoint Function Driver to implement Non-Transparent Bridge functionality
10 * The PCI NTB function driver configures the SoC with multiple PCIe Endpoint
16 * +-------------+ +-------------+
20 * +------^------+ +------^------+
23 * +---------|-------------------------------------------------|---------+
24 * | +------v------+ +------v------+ |
28 * | | <-----------------------------------> | |
33 * | +-------------+ +-------------+ |
34 * +---------------------------------------------------------------------+
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Dpci-epf-vntb.c1 // SPDX-License-Identifier: GPL-2.0
3 * Endpoint Function Driver to implement Non-Transparent Bridge functionality
9 * Based on pci-epf-ntb.c
15 * +------------+ +---------------------------------------+
17 * +------------+ | +--------------+
20 * +------------+ | +--------------+
23 * +------------+ | +--------------+
28 * | | +---------------+ | NTB Driver |
29 * | | | PCI EP NTB |<------>| |
31 * +------------+ +---------------+ +--------------+
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/Linux-v6.1/arch/arm/boot/dts/
Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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Duniphier-pro5.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "socionext,uniphier-pro5";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
24 enable-method = "psci";
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Ddra7.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
21 interrupt-parent = <&crossbar_mpu>;
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/Linux-v6.1/drivers/rapidio/devices/
Dtsi721.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Tsi721 PCIExpress-to-SRIO bridge definitions
93 * Registers in PCIe configuration space
116 * Port-Write Block Registers
167 #define TSI721_IDQ_SIZE_VAL(size) (__fls(size) - 4)
191 #define TSI721_IBWIN_SIZE(size) (__fls(size) - 12)
236 #define TSI721_OBWIN_SIZE(size) (__fls(size) - 15)
314 #define TSI721_DMAC_DSSZ_SIZE(size) (__fls(size) - 4)
633 DTYPE5 = 5, /* OB Messaging Block Pointer Descriptor */
677 /* low 64-bits of 66-bit RIO address */
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Dtsi721.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * RapidIO mport driver for Tsi721 PCIExpress-to-SRIO bridge
19 #include <linux/dma-mapping.h>
32 static int pcie_mrrs = -1;
34 MODULE_PARM_DESC(pcie_mrrs, "PCIe MRRS override value (0...5)");
47 * tsi721_lcread - read from local SREP config space
55 * success or %-EINVAL on failure.
60 struct tsi721_device *priv = mport->priv; in tsi721_lcread()
63 return -EINVAL; /* only 32-bit access is supported */ in tsi721_lcread()
65 *data = ioread32(priv->regs + offset); in tsi721_lcread()
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/Linux-v6.1/drivers/phy/mscc/
Dphy-ocelot-serdes.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
19 #include <dt-bindings/phy/phy-ocelot-serdes.h>
29 /* Not used when in QSGMII or PCIe mode */
150 /* OB + DES + IB + SER CFG */ in serdes_init_s6g()
406 return -EOPNOTSUPP; in serdes_set_mode()
409 if (macro->idx != ocelot_serdes_muxes[i].idx || in serdes_set_mode()
415 macro->port != ocelot_serdes_muxes[i].port) in serdes_set_mode()
418 ret = regmap_update_bits(macro->ctrl->regs, HSIO_HW_CFG, in serdes_set_mode()
424 if (macro->idx <= SERDES1G_MAX) in serdes_set_mode()
425 return serdes_init_s1g(macro->ctrl->regs, macro->idx); in serdes_set_mode()
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/Linux-v6.1/arch/arm64/boot/dts/ti/
Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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/Linux-v6.1/arch/arm64/boot/dts/nvidia/
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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/Linux-v6.1/
DCREDITS1 This is at least a partial credits-file of people that have
4 scripts. The fields are: name (N), email (E), web-address
6 snail-mail address (S).
10 ----------
51 D: in-kernel DRM Maintainer
71 E: tim_alpaerts@toyota-motor-europe.com
75 S: B-2610 Wilrijk-Antwerpen
80 W: http://www-stu.christs.cam.ac.uk/~aia21/
101 D: Maintainer of ide-cd and Uniform CD-ROM driver,
102 D: ATAPI CD-Changer support, Major 2.1.x CD-ROM update.
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