Lines Matching +full:pcie +full:- +full:ob
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
16 clock-names = "sata", "pmalive", "rxoob";
19 phy-names = "sata-phy";
20 ports-implemented = <0x1>;
21 power-domains = <&power RK3568_PD_PIPE>;
26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
31 compatible = "rockchip,rk3568-qos", "syscon";
36 compatible = "rockchip,rk3568-qos", "syscon";
41 compatible = "rockchip,rk3568-qos", "syscon";
46 compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
51 compatible = "rockchip,rk3568-pcie3-phy";
53 #phy-cells = <0>;
56 clock-names = "refclk_m", "refclk_n", "pclk";
58 reset-names = "phy";
59 rockchip,phy-grf = <&pcie30_phy_grf>;
63 pcie3x1: pcie@fe270000 {
64 compatible = "rockchip,rk3568-pcie";
65 #address-cells = <3>;
66 #size-cells = <2>;
67 bus-range = <0x0 0xf>;
71 clock-names = "aclk_mst", "aclk_slv",
79 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
80 #interrupt-cells = <1>;
81 interrupt-map-mask = <0 0 0 7>;
82 interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
86 linux,pci-domain = <1>;
87 num-ib-windows = <6>;
88 num-ob-windows = <2>;
89 max-link-speed = <3>;
90 msi-map = <0x0 &gic 0x1000 0x1000>;
91 num-lanes = <1>;
93 phy-names = "pcie-phy";
94 power-domains = <&power RK3568_PD_PIPE>;
100 reg-names = "dbi", "apb", "config";
102 reset-names = "pipe";
106 pcie3x1_intc: legacy-interrupt-controller {
107 interrupt-controller;
108 #address-cells = <0>;
109 #interrupt-cells = <1>;
110 interrupt-parent = <&gic>;
115 pcie3x2: pcie@fe280000 {
116 compatible = "rockchip,rk3568-pcie";
117 #address-cells = <3>;
118 #size-cells = <2>;
119 bus-range = <0x0 0xf>;
123 clock-names = "aclk_mst", "aclk_slv",
131 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
132 #interrupt-cells = <1>;
133 interrupt-map-mask = <0 0 0 7>;
134 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
138 linux,pci-domain = <2>;
139 num-ib-windows = <6>;
140 num-ob-windows = <2>;
141 max-link-speed = <3>;
142 msi-map = <0x0 &gic 0x2000 0x1000>;
143 num-lanes = <2>;
145 phy-names = "pcie-phy";
146 power-domains = <&power RK3568_PD_PIPE>;
152 reg-names = "dbi", "apb", "config";
154 reset-names = "pipe";
158 pcie3x2_intc: legacy-interrupt-controller {
159 interrupt-controller;
160 #address-cells = <0>;
161 #interrupt-cells = <1>;
162 interrupt-parent = <&gic>;
168 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
172 interrupt-names = "macirq", "eth_wake_irq";
177 clock-names = "stmmaceth", "mac_clk_rx",
182 reset-names = "stmmaceth";
184 snps,axi-config = <&gmac0_stmmac_axi_setup>;
185 snps,mixed-burst;
186 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
187 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
192 compatible = "snps,dwmac-mdio";
193 #address-cells = <0x1>;
194 #size-cells = <0x0>;
197 gmac0_stmmac_axi_setup: stmmac-axi-config {
203 gmac0_mtl_rx_setup: rx-queues-config {
204 snps,rx-queues-to-use = <1>;
208 gmac0_mtl_tx_setup: tx-queues-config {
209 snps,tx-queues-to-use = <1>;
215 compatible = "rockchip,rk3568-naneng-combphy";
220 clock-names = "ref", "apb", "pipe";
221 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
222 assigned-clock-rates = <100000000>;
224 rockchip,pipe-grf = <&pipegrf>;
225 rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
226 #phy-cells = <1>;
232 opp-1992000000 {
233 opp-hz = /bits/ 64 <1992000000>;
234 opp-microvolt = <1150000 1150000 1150000>;
239 compatible = "rockchip,rk3568-pipe-grf", "syscon";
243 power-domain@RK3568_PD_PIPE {
254 #power-domain-cells = <0>;
260 phy-names = "usb2-phy", "usb3-phy";
264 compatible = "rockchip,rk3568-vop";