Lines Matching +full:pcie +full:- +full:ob
1 // SPDX-License-Identifier: GPL-2.0
3 * Synopsys DesignWare PCIe host controller driver
20 #include "pcie-designware.h"
26 /* The content of the CSR is zero on DWC PCIe older than v4.70a */ in dw_pcie_version_detect()
31 if (pci->version && pci->version != ver) in dw_pcie_version_detect()
32 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n", in dw_pcie_version_detect()
33 pci->version, ver); in dw_pcie_version_detect()
35 pci->version = ver; in dw_pcie_version_detect()
39 if (pci->type && pci->type != ver) in dw_pcie_version_detect()
40 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n", in dw_pcie_version_detect()
41 pci->type, ver); in dw_pcie_version_detect()
43 pci->type = ver; in dw_pcie_version_detect()
93 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; in dw_pcie_find_next_ext_capability()
106 while (ttl-- > 0) { in dw_pcie_find_next_ext_capability()
171 if (pci->ops && pci->ops->read_dbi) in dw_pcie_read_dbi()
172 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); in dw_pcie_read_dbi()
174 ret = dw_pcie_read(pci->dbi_base + reg, size, &val); in dw_pcie_read_dbi()
176 dev_err(pci->dev, "Read DBI address failed\n"); in dw_pcie_read_dbi()
186 if (pci->ops && pci->ops->write_dbi) { in dw_pcie_write_dbi()
187 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); in dw_pcie_write_dbi()
191 ret = dw_pcie_write(pci->dbi_base + reg, size, val); in dw_pcie_write_dbi()
193 dev_err(pci->dev, "Write DBI address failed\n"); in dw_pcie_write_dbi()
201 if (pci->ops && pci->ops->write_dbi2) { in dw_pcie_write_dbi2()
202 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); in dw_pcie_write_dbi2()
206 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); in dw_pcie_write_dbi2()
208 dev_err(pci->dev, "write DBI address failed\n"); in dw_pcie_write_dbi2()
214 if (pci->iatu_unroll_enabled) in dw_pcie_select_atu()
215 return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index); in dw_pcie_select_atu()
218 return pci->atu_base; in dw_pcie_select_atu()
229 if (pci->ops && pci->ops->read_dbi) in dw_pcie_readl_atu()
230 return pci->ops->read_dbi(pci, base, reg, 4); in dw_pcie_readl_atu()
234 dev_err(pci->dev, "Read ATU address failed\n"); in dw_pcie_readl_atu()
247 if (pci->ops && pci->ops->write_dbi) { in dw_pcie_writel_atu()
248 pci->ops->write_dbi(pci, base, reg, 4, val); in dw_pcie_writel_atu()
254 dev_err(pci->dev, "Write ATU address failed\n"); in dw_pcie_writel_atu()
272 * bit in the Control register-1 of the ATU outbound region acts in dw_pcie_enable_ecrc()
275 * bit. This is contrary to the PCIe spec which says that the in dw_pcie_enable_ecrc()
291 * on Root Port:- TLP Digest (DWord size) gets appended to each packet in dw_pcie_enable_ecrc()
296 * on End Point:- TLP Digest is received for some/all the packets coming in dw_pcie_enable_ecrc()
298 * as per the PCIe Spec r5.0 v1.0 section 2.2.3 in dw_pcie_enable_ecrc()
316 if (pci->ops && pci->ops->cpu_addr_fixup) in __dw_pcie_prog_outbound_atu()
317 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); in __dw_pcie_prog_outbound_atu()
319 limit_addr = cpu_addr + size - 1; in __dw_pcie_prog_outbound_atu()
321 if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) || in __dw_pcie_prog_outbound_atu()
322 !IS_ALIGNED(cpu_addr, pci->region_align) || in __dw_pcie_prog_outbound_atu()
323 !IS_ALIGNED(pci_addr, pci->region_align) || !size) { in __dw_pcie_prog_outbound_atu()
324 return -EINVAL; in __dw_pcie_prog_outbound_atu()
365 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); in __dw_pcie_prog_outbound_atu()
367 return -ETIMEDOUT; in __dw_pcie_prog_outbound_atu()
401 if (!IS_ALIGNED(cpu_addr, pci->region_align)) in dw_pcie_prog_inbound_atu()
402 return -EINVAL; in dw_pcie_prog_inbound_atu()
427 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_inbound_atu()
429 return -ETIMEDOUT; in dw_pcie_prog_inbound_atu()
451 dev_err(pci->dev, "Phy link never came up\n"); in dw_pcie_wait_for_link()
452 return -ETIMEDOUT; in dw_pcie_wait_for_link()
458 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", in dw_pcie_wait_for_link()
470 if (pci->ops && pci->ops->link_up) in dw_pcie_link_up()
471 return pci->ops->link_up(pci); in dw_pcie_link_up()
538 int max_region, ob, ib; in dw_pcie_iatu_detect_regions() local
542 if (pci->iatu_unroll_enabled) { in dw_pcie_iatu_detect_regions()
543 max_region = min((int)pci->atu_size / 512, 256); in dw_pcie_iatu_detect_regions()
549 for (ob = 0; ob < max_region; ob++) { in dw_pcie_iatu_detect_regions()
550 dw_pcie_writel_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET, 0x11110000); in dw_pcie_iatu_detect_regions()
551 val = dw_pcie_readl_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET); in dw_pcie_iatu_detect_regions()
563 if (ob) { in dw_pcie_iatu_detect_regions()
568 dev_err(pci->dev, "No iATU regions found\n"); in dw_pcie_iatu_detect_regions()
582 pci->num_ob_windows = ob; in dw_pcie_iatu_detect_regions()
583 pci->num_ib_windows = ib; in dw_pcie_iatu_detect_regions()
584 pci->region_align = 1 << fls(min); in dw_pcie_iatu_detect_regions()
585 pci->region_limit = (max << 32) | (SZ_4G - 1); in dw_pcie_iatu_detect_regions()
590 struct platform_device *pdev = to_platform_device(pci->dev); in dw_pcie_iatu_detect()
592 pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); in dw_pcie_iatu_detect()
593 if (pci->iatu_unroll_enabled) { in dw_pcie_iatu_detect()
594 if (!pci->atu_base) { in dw_pcie_iatu_detect()
598 pci->atu_size = resource_size(res); in dw_pcie_iatu_detect()
599 pci->atu_base = devm_ioremap_resource(pci->dev, res); in dw_pcie_iatu_detect()
601 if (!pci->atu_base || IS_ERR(pci->atu_base)) in dw_pcie_iatu_detect()
602 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; in dw_pcie_iatu_detect()
605 if (!pci->atu_size) in dw_pcie_iatu_detect()
607 pci->atu_size = SZ_4K; in dw_pcie_iatu_detect()
609 pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE; in dw_pcie_iatu_detect()
610 pci->atu_size = PCIE_ATU_VIEWPORT_SIZE; in dw_pcie_iatu_detect()
615 dev_info(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? in dw_pcie_iatu_detect()
618 dev_info(pci->dev, "iATU regions: %u ob, %u ib, align %uK, limit %lluG\n", in dw_pcie_iatu_detect()
619 pci->num_ob_windows, pci->num_ib_windows, in dw_pcie_iatu_detect()
620 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G); in dw_pcie_iatu_detect()
625 struct device_node *np = pci->dev->of_node; in dw_pcie_setup()
628 if (pci->link_gen > 0) in dw_pcie_setup()
629 dw_pcie_link_set_max_speed(pci, pci->link_gen); in dw_pcie_setup()
632 if (pci->n_fts[0]) { in dw_pcie_setup()
635 val |= PORT_AFR_N_FTS(pci->n_fts[0]); in dw_pcie_setup()
636 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]); in dw_pcie_setup()
641 if (pci->n_fts[1]) { in dw_pcie_setup()
644 val |= pci->n_fts[pci->link_gen - 1]; in dw_pcie_setup()
653 if (of_property_read_bool(np, "snps,enable-cdm-check")) { in dw_pcie_setup()
660 of_property_read_u32(np, "num-lanes", &pci->num_lanes); in dw_pcie_setup()
661 if (!pci->num_lanes) { in dw_pcie_setup()
662 dev_dbg(pci->dev, "Using h/w default number of lanes\n"); in dw_pcie_setup()
669 switch (pci->num_lanes) { in dw_pcie_setup()
683 dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes); in dw_pcie_setup()
691 switch (pci->num_lanes) { in dw_pcie_setup()