Lines Matching +full:pcie +full:- +full:ob
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Tsi721 PCIExpress-to-SRIO bridge definitions
93 * Registers in PCIe configuration space
116 * Port-Write Block Registers
167 #define TSI721_IDQ_SIZE_VAL(size) (__fls(size) - 4)
191 #define TSI721_IBWIN_SIZE(size) (__fls(size) - 12)
236 #define TSI721_OBWIN_SIZE(size) (__fls(size) - 15)
314 #define TSI721_DMAC_DSSZ_SIZE(size) (__fls(size) - 4)
633 DTYPE5 = 5, /* OB Messaging Block Pointer Descriptor */
677 /* low 64-bits of 66-bit RIO address */
679 /* upper 2-bits of 66-bit RIO address */
746 /* VA/PA of OB Msg descriptors */
749 /* VA/PA of OB Msg data buffers */
752 /* VA/PA of OB Msg descriptor status FIFO */
772 * MSI-X Table Entries (0 ... 69)
789 /* MSI-X vector and init table entry indexes */
882 /* Inbound Port-Write */