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/Linux-v5.15/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,disp.txt4 The Mediatek display subsystem consists of various DISP function blocks in the
10 All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
14 DISP function blocks
19 interface, or writes pixels back to memory. All DISP function blocks have
29 - compatible: "mediatek,<chip>-disp-<function>", one of
30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33 "mediatek,<chip>-disp-wdma" - write DMA
34 "mediatek,<chip>-disp-ccorr" - color correction
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/Linux-v5.15/Documentation/devicetree/bindings/pwm/
Dpwm-mtk-disp.txt4 - compatible: should be "mediatek,<name>-disp-pwm":
5 - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
6 - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
7 - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC.
8 - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
9 - reg: physical base address and length of the controller's registers.
10 - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
12 - clocks: phandle and clock specifier of the PWM reference clock.
13 - clock-names: must contain the following:
14 - "main": clock used to generate PWM signals.
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/Linux-v5.15/drivers/gpu/drm/mediatek/
Dmtk_drm_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/dma-mapping.h>
49 if (info->num_planes != 1) in mtk_drm_mode_fb_create()
50 return ERR_PTR(-EINVAL); in mtk_drm_mode_fb_create()
207 struct mtk_drm_private *private = drm->dev_private; in mtk_drm_kms_init()
214 return -EPROBE_DEFER; in mtk_drm_kms_init()
216 pdev = of_find_device_by_node(private->mutex_node); in mtk_drm_kms_init()
218 dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n", in mtk_drm_kms_init()
219 private->mutex_node); in mtk_drm_kms_init()
220 of_node_put(private->mutex_node); in mtk_drm_kms_init()
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Dmtk_disp_color.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/soc/mediatek/mtk-cmdq.h>
22 #define DISP_COLOR_START(comp) ((comp)->data->color_offset)
34 * struct mtk_disp_color - DISP_COLOR driver structure
50 return clk_prepare_enable(color->clk); in mtk_color_clk_enable()
57 clk_disable_unprepare(color->clk); in mtk_color_clk_disable()
66 mtk_ddp_write(cmdq_pkt, w, &color->cmdq_reg, color->regs, DISP_COLOR_WIDTH(color)); in mtk_color_config()
67 mtk_ddp_write(cmdq_pkt, h, &color->cmdq_reg, color->regs, DISP_COLOR_HEIGHT(color)); in mtk_color_config()
75 color->regs + DISP_COLOR_CFG_MAIN); in mtk_color_start()
76 writel(0x1, color->regs + DISP_COLOR_START(color)); in mtk_color_start()
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Dmtk_disp_aal.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/soc/mediatek/mtk-cmdq.h>
29 * struct mtk_disp_aal - DISP_AAL driver structure
30 * @ddp_comp - structure containing type enum and hardware resources
31 * @crtc - associated crtc to report irq events to
44 return clk_prepare_enable(aal->clk); in mtk_aal_clk_enable()
51 clk_disable_unprepare(aal->clk); in mtk_aal_clk_disable()
60 mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); in mtk_aal_config()
61 mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); in mtk_aal_config()
68 if (aal->data && aal->data->has_gamma) in mtk_aal_gamma_set()
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Dmtk_disp_gamma.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/soc/mediatek/mtk-cmdq.h>
33 * struct mtk_disp_gamma - DISP_GAMMA driver structure
46 return clk_prepare_enable(gamma->clk); in mtk_gamma_clk_enable()
53 clk_disable_unprepare(gamma->clk); in mtk_gamma_clk_disable()
63 if (state->gamma_lut) { in mtk_gamma_set_common()
68 lut = (struct drm_color_lut *)state->gamma_lut->data; in mtk_gamma_set_common()
82 mtk_gamma_set_common(gamma->regs, state); in mtk_gamma_set()
91 mtk_ddp_write(cmdq_pkt, h << 16 | w, &gamma->cmdq_reg, gamma->regs, in mtk_gamma_config()
93 if (gamma->data && gamma->data->has_dither) in mtk_gamma_config()
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Dmtk_disp_rdma.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/soc/mediatek/mtk-cmdq.h>
49 #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size)
59 * struct mtk_disp_rdma - DISP_RDMA driver structure
77 writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS); in mtk_disp_rdma_irq_handler()
79 if (!priv->vblank_cb) in mtk_disp_rdma_irq_handler()
82 priv->vblank_cb(priv->vblank_cb_data); in mtk_disp_rdma_irq_handler()
91 unsigned int tmp = readl(rdma->regs + reg); in rdma_update_bits()
94 writel(tmp, rdma->regs + reg); in rdma_update_bits()
103 rdma->vblank_cb = vblank_cb; in mtk_rdma_enable_vblank()
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Dmtk_disp_ovl.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/soc/mediatek/mtk-cmdq.h>
39 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n))
52 #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
54 #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
70 * struct mtk_disp_ovl - DISP_OVL driver structure
89 writel(0x0, priv->regs + DISP_REG_OVL_INTSTA); in mtk_disp_ovl_irq_handler()
91 if (!priv->vblank_cb) in mtk_disp_ovl_irq_handler()
94 priv->vblank_cb(priv->vblank_cb_data); in mtk_disp_ovl_irq_handler()
105 ovl->vblank_cb = vblank_cb; in mtk_ovl_enable_vblank()
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/Linux-v5.15/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/memory/mt8173-larb-port.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/power/mt8173-power.h>
20 #include <dt-bindings/reset/mt8173-resets.h>
21 #include <dt-bindings/gce/mt8173-gce.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include "mt8173-pinfunc.h"
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Dmt8183.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8183-larb-port.h>
13 #include <dt-bindings/power/mt8183-power.h>
14 #include <dt-bindings/reset-controller/mt8183-resets.h>
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/thermal/thermal.h>
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/Linux-v5.15/arch/arm/boot/dts/
Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
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Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
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/Linux-v5.15/Documentation/devicetree/bindings/mailbox/
Dmtk-gce.txt9 mailbox.txt for generic information about mailbox device-tree bindings.
12 - compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce",
13 "mediatek,mt8192-gce", "mediatek,mt8195-gce" or "mediatek,mt6779-gce".
14 - reg: Address range of the GCE unit
15 - interrupts: The interrupt signal from the GCE block
16 - clock: Clocks according to the common clock binding
17 - clock-names: Must be "gce" to stand for GCE clock
18 - #mbox-cells: Should be 2.
25 - mboxes: Client use mailbox to communicate with GCE, it should have this
28 - mediatek,gce-client-reg: Specify the sub-system id which is corresponding
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/Linux-v5.15/Documentation/devicetree/bindings/iommu/
Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
31 +--------+
35 +----------------+-------
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/Linux-v5.15/drivers/pwm/
Dpwm-mtk-disp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MediaTek display pulse-width-modulation controller driver.
26 #define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
62 void __iomem *address = mdp->base + offset; in mtk_disp_pwm_update_bits()
79 if (state->polarity != PWM_POLARITY_NORMAL) in mtk_disp_pwm_apply()
80 return -EINVAL; in mtk_disp_pwm_apply()
82 if (!state->enabled) { in mtk_disp_pwm_apply()
83 mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, in mtk_disp_pwm_apply()
86 if (mdp->enabled) { in mtk_disp_pwm_apply()
87 clk_disable_unprepare(mdp->clk_mm); in mtk_disp_pwm_apply()
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/Linux-v5.15/drivers/soc/mediatek/
Dmtk-mutex.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/soc/mediatek/mtk-mmsys.h>
13 #include <linux/soc/mediatek/mtk-mutex.h>
284 if (!mtx->mutex[i].claimed) { in mtk_mutex_get()
285 mtx->mutex[i].claimed = true; in mtk_mutex_get()
286 return &mtx->mutex[i]; in mtk_mutex_get()
289 return ERR_PTR(-EBUSY); in mtk_mutex_get()
296 mutex[mutex->id]); in mtk_mutex_put()
298 WARN_ON(&mtx->mutex[mutex->id] != mutex); in mtk_mutex_put()
300 mutex->claimed = false; in mtk_mutex_put()
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Dmtk-scpsys.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <dt-bindings/power/mt2701-power.h>
17 #include <dt-bindings/power/mt2712-power.h>
18 #include <dt-bindings/power/mt6797-power.h>
19 #include <dt-bindings/power/mt7622-power.h>
20 #include <dt-bindings/power/mt7623a-power.h>
21 #include <dt-bindings/power/mt8173-power.h>
28 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
37 #define SPM_AUDIO_PWR_CON 0x029c /* MT8173, MT2712 */
72 #define PWR_STATUS_MFG_2D BIT(22) /* MT8173 */
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/Linux-v5.15/drivers/iommu/
Dmtk_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
11 #include <linux/dma-direct.h>
123 ((((pdata)->flags) & (_x)) == (_x))
149 * |---A---|---B---|---C---|---D---|---E---|
150 * +--I/O--+------------Memory-------------+
156 * |---E---|---B---|---C---|---D---|
157 * +------------Memory-------------+
180 { .iova_base = 0x0, .size = SZ_4G}, /* disp: 0 ~ 4G */
214 if (pm_runtime_get_if_in_use(data->dev) <= 0) in mtk_iommu_tlb_flush_all()
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