1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/soc/mediatek/mtk-cmdq.h>
39 #define DISP_REG_OVL_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n))
52 #define OVL_CON_CLRFMT_RGB565(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \
54 #define OVL_CON_CLRFMT_RGB888(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \
70  * struct mtk_disp_ovl - DISP_OVL driver structure
89 	writel(0x0, priv->regs + DISP_REG_OVL_INTSTA);  in mtk_disp_ovl_irq_handler()
91 	if (!priv->vblank_cb)  in mtk_disp_ovl_irq_handler()
94 	priv->vblank_cb(priv->vblank_cb_data);  in mtk_disp_ovl_irq_handler()
105 	ovl->vblank_cb = vblank_cb;  in mtk_ovl_enable_vblank()
106 	ovl->vblank_cb_data = vblank_cb_data;  in mtk_ovl_enable_vblank()
107 	writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);  in mtk_ovl_enable_vblank()
108 	writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN);  in mtk_ovl_enable_vblank()
115 	ovl->vblank_cb = NULL;  in mtk_ovl_disable_vblank()
116 	ovl->vblank_cb_data = NULL;  in mtk_ovl_disable_vblank()
117 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);  in mtk_ovl_disable_vblank()
124 	return clk_prepare_enable(ovl->clk);  in mtk_ovl_clk_enable()
131 	clk_disable_unprepare(ovl->clk);  in mtk_ovl_clk_disable()
138 	if (ovl->data->smi_id_en) {  in mtk_ovl_start()
141 		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_start()
143 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_start()
145 	writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);  in mtk_ovl_start()
152 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);  in mtk_ovl_stop()
153 	if (ovl->data->smi_id_en) {  in mtk_ovl_stop()
156 		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_stop()
158 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_stop()
170 		mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_config()
172 	mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR);  in mtk_ovl_config()
174 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);  in mtk_ovl_config()
175 	mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);  in mtk_ovl_config()
182 	return ovl->data->layer_nr;  in mtk_ovl_layer_nr()
194 	struct drm_plane_state *state = &mtk_state->base;  in mtk_ovl_layer_check()
197 	rotation = drm_rotation_simplify(state->rotation,  in mtk_ovl_layer_check()
205 		return -EINVAL;  in mtk_ovl_layer_check()
211 	if (state->fb->format->is_yuv && rotation != 0)  in mtk_ovl_layer_check()
212 		return -EINVAL;  in mtk_ovl_layer_check()
214 	state->rotation = rotation;  in mtk_ovl_layer_check()
227 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_on()
230 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);  in mtk_ovl_layer_on()
232 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);  in mtk_ovl_layer_on()
233 	if (ovl->data->gmc_bits == 10)  in mtk_ovl_layer_on()
239 		      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));  in mtk_ovl_layer_on()
240 	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_on()
249 	mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_off()
251 	mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_off()
296 	struct mtk_plane_pending_state *pending = &state->pending;  in mtk_ovl_layer_config()
297 	unsigned int addr = pending->addr;  in mtk_ovl_layer_config()
298 	unsigned int pitch = pending->pitch & 0xffff;  in mtk_ovl_layer_config()
299 	unsigned int fmt = pending->format;  in mtk_ovl_layer_config()
300 	unsigned int offset = (pending->y << 16) | pending->x;  in mtk_ovl_layer_config()
301 	unsigned int src_size = (pending->height << 16) | pending->width;  in mtk_ovl_layer_config()
304 	if (!pending->enable) {  in mtk_ovl_layer_config()
310 	if (state->base.fb && state->base.fb->format->has_alpha)  in mtk_ovl_layer_config()
313 	if (pending->rotation & DRM_MODE_REFLECT_Y) {  in mtk_ovl_layer_config()
315 		addr += (pending->height - 1) * pending->pitch;  in mtk_ovl_layer_config()
318 	if (pending->rotation & DRM_MODE_REFLECT_X) {  in mtk_ovl_layer_config()
320 		addr += pending->pitch - 1;  in mtk_ovl_layer_config()
323 	mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
325 	mtk_ddp_write_relaxed(cmdq_pkt, pitch, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
327 	mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
329 	mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
331 	mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
342 	reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_on()
344 	writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_on()
352 	reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_off()
354 	writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_off()
375 	struct device *dev = &pdev->dev;  in mtk_disp_ovl_probe()
383 		return -ENOMEM;  in mtk_disp_ovl_probe()
389 	priv->clk = devm_clk_get(dev, NULL);  in mtk_disp_ovl_probe()
390 	if (IS_ERR(priv->clk)) {  in mtk_disp_ovl_probe()
392 		return PTR_ERR(priv->clk);  in mtk_disp_ovl_probe()
396 	priv->regs = devm_ioremap_resource(dev, res);  in mtk_disp_ovl_probe()
397 	if (IS_ERR(priv->regs)) {  in mtk_disp_ovl_probe()
399 		return PTR_ERR(priv->regs);  in mtk_disp_ovl_probe()
402 	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);  in mtk_disp_ovl_probe()
404 		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");  in mtk_disp_ovl_probe()
407 	priv->data = of_device_get_match_data(dev);  in mtk_disp_ovl_probe()
426 	component_del(&pdev->dev, &mtk_disp_ovl_component_ops);  in mtk_disp_ovl_remove()
460 	{ .compatible = "mediatek,mt2701-disp-ovl",
462 	{ .compatible = "mediatek,mt8173-disp-ovl",
464 	{ .compatible = "mediatek,mt8183-disp-ovl",
466 	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
476 		.name	= "mediatek-disp-ovl",