Lines Matching +full:mt8173 +full:- +full:disp
1 // SPDX-License-Identifier: GPL-2.0-only
3 * MediaTek display pulse-width-modulation controller driver.
26 #define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
62 void __iomem *address = mdp->base + offset; in mtk_disp_pwm_update_bits()
79 if (state->polarity != PWM_POLARITY_NORMAL) in mtk_disp_pwm_apply()
80 return -EINVAL; in mtk_disp_pwm_apply()
82 if (!state->enabled) { in mtk_disp_pwm_apply()
83 mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, in mtk_disp_pwm_apply()
86 if (mdp->enabled) { in mtk_disp_pwm_apply()
87 clk_disable_unprepare(mdp->clk_mm); in mtk_disp_pwm_apply()
88 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_apply()
91 mdp->enabled = false; in mtk_disp_pwm_apply()
95 if (!mdp->enabled) { in mtk_disp_pwm_apply()
96 err = clk_prepare_enable(mdp->clk_main); in mtk_disp_pwm_apply()
98 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", in mtk_disp_pwm_apply()
103 err = clk_prepare_enable(mdp->clk_mm); in mtk_disp_pwm_apply()
105 dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", in mtk_disp_pwm_apply()
107 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_apply()
119 * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1 in mtk_disp_pwm_apply()
122 rate = clk_get_rate(mdp->clk_main); in mtk_disp_pwm_apply()
123 clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >> in mtk_disp_pwm_apply()
126 if (!mdp->enabled) { in mtk_disp_pwm_apply()
127 clk_disable_unprepare(mdp->clk_mm); in mtk_disp_pwm_apply()
128 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_apply()
130 return -EINVAL; in mtk_disp_pwm_apply()
134 period = mul_u64_u64_div_u64(state->period, rate, div); in mtk_disp_pwm_apply()
136 period--; in mtk_disp_pwm_apply()
138 high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div); in mtk_disp_pwm_apply()
141 mtk_disp_pwm_update_bits(mdp, mdp->data->con0, in mtk_disp_pwm_apply()
144 mtk_disp_pwm_update_bits(mdp, mdp->data->con1, in mtk_disp_pwm_apply()
148 if (mdp->data->has_commit) { in mtk_disp_pwm_apply()
149 mtk_disp_pwm_update_bits(mdp, mdp->data->commit, in mtk_disp_pwm_apply()
150 mdp->data->commit_mask, in mtk_disp_pwm_apply()
151 mdp->data->commit_mask); in mtk_disp_pwm_apply()
152 mtk_disp_pwm_update_bits(mdp, mdp->data->commit, in mtk_disp_pwm_apply()
153 mdp->data->commit_mask, in mtk_disp_pwm_apply()
160 mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug, in mtk_disp_pwm_apply()
161 mdp->data->bls_debug_mask, in mtk_disp_pwm_apply()
162 mdp->data->bls_debug_mask); in mtk_disp_pwm_apply()
163 mtk_disp_pwm_update_bits(mdp, mdp->data->con0, in mtk_disp_pwm_apply()
164 mdp->data->con0_sel, in mtk_disp_pwm_apply()
165 mdp->data->con0_sel); in mtk_disp_pwm_apply()
168 mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, in mtk_disp_pwm_apply()
169 mdp->data->enable_mask); in mtk_disp_pwm_apply()
170 mdp->enabled = true; in mtk_disp_pwm_apply()
184 err = clk_prepare_enable(mdp->clk_main); in mtk_disp_pwm_get_state()
186 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); in mtk_disp_pwm_get_state()
190 err = clk_prepare_enable(mdp->clk_mm); in mtk_disp_pwm_get_state()
192 dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err)); in mtk_disp_pwm_get_state()
193 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_get_state()
197 rate = clk_get_rate(mdp->clk_main); in mtk_disp_pwm_get_state()
198 con0 = readl(mdp->base + mdp->data->con0); in mtk_disp_pwm_get_state()
199 con1 = readl(mdp->base + mdp->data->con1); in mtk_disp_pwm_get_state()
200 state->enabled = !!(con0 & BIT(0)); in mtk_disp_pwm_get_state()
207 state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate); in mtk_disp_pwm_get_state()
209 state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC, in mtk_disp_pwm_get_state()
211 state->polarity = PWM_POLARITY_NORMAL; in mtk_disp_pwm_get_state()
212 clk_disable_unprepare(mdp->clk_mm); in mtk_disp_pwm_get_state()
213 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_get_state()
227 mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL); in mtk_disp_pwm_probe()
229 return -ENOMEM; in mtk_disp_pwm_probe()
231 mdp->data = of_device_get_match_data(&pdev->dev); in mtk_disp_pwm_probe()
233 mdp->base = devm_platform_ioremap_resource(pdev, 0); in mtk_disp_pwm_probe()
234 if (IS_ERR(mdp->base)) in mtk_disp_pwm_probe()
235 return PTR_ERR(mdp->base); in mtk_disp_pwm_probe()
237 mdp->clk_main = devm_clk_get(&pdev->dev, "main"); in mtk_disp_pwm_probe()
238 if (IS_ERR(mdp->clk_main)) in mtk_disp_pwm_probe()
239 return PTR_ERR(mdp->clk_main); in mtk_disp_pwm_probe()
241 mdp->clk_mm = devm_clk_get(&pdev->dev, "mm"); in mtk_disp_pwm_probe()
242 if (IS_ERR(mdp->clk_mm)) in mtk_disp_pwm_probe()
243 return PTR_ERR(mdp->clk_mm); in mtk_disp_pwm_probe()
245 mdp->chip.dev = &pdev->dev; in mtk_disp_pwm_probe()
246 mdp->chip.ops = &mtk_disp_pwm_ops; in mtk_disp_pwm_probe()
247 mdp->chip.npwm = 1; in mtk_disp_pwm_probe()
249 ret = pwmchip_add(&mdp->chip); in mtk_disp_pwm_probe()
251 dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret)); in mtk_disp_pwm_probe()
264 pwmchip_remove(&mdp->chip); in mtk_disp_pwm_remove()
300 { .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
301 { .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
302 { .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
303 { .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
310 .name = "mediatek-disp-pwm",