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/Linux-v5.10/arch/arm/boot/dts/
Dintegratorap-im-pd1.dts1 // SPDX-License-Identifier: GPL-2.0
4 * with the IM-PD1 example logical module mounted.
10 model = "ARM Integrator/AP with IM-PD1";
11 compatible = "arm,integrator-ap";
13 reserved-memory {
14 #address-cells = <1>;
15 #size-cells = <1>;
19 /* 1 MB of designated video RAM on the IM-PD1 */
20 compatible = "shared-dma-pool";
22 no-map;
[all …]
Dste-href-tvk1281618-r2.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "ste-href-tvk1281618.dtsi"
13 compatible = "st,lsm303dlh-accel";
14 st,drdy-int-pin = <1>;
15 drive-open-drain;
17 vdd-supply = <&ab8500_ldo_aux1_reg>;
18 vddio-supply = <&db8500_vsmps2_reg>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&accel_tvk_mode>;
22 * These interrupts cannot be used: the other component
[all …]
Domap3-evm-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/input/input.h>
7 #include "omap-gpmc-smsc911x.dtsi"
12 cpu0-supply = <&vcc>;
18 compatible = "regulator-fixed";
19 regulator-name = "hsusb2_vbus";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
23 startup-delay-us = <70000>;
24 enable-active-high;
[all …]
Dmotorola-cpcap-mapphone.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 interrupt-parent = <&gpio1>;
11 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
12 interrupt-controller;
13 #interrupt-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 spi-max-frequency = <9600000>;
17 spi-cs-high;
18 spi-cpol;
[all …]
Darmada-38x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
37 compatible = "marvell,armada380-mbus", "simple-bus";
[all …]
Dste-href-tvk1281618.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 ST-Ericsson AB
8 #include <dt-bindings/interrupt-controller/irq.h>
12 compatible = "gpio-keys";
13 #address-cells = <1>;
14 #size-cells = <0>;
15 vdd-supply = <&ab8500_ldo_aux1_reg>;
16 pinctrl-names = "default";
17 pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>;
38 interrupt-parent = <&gpio6>;
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
[all …]
Dsamsung,exynos4210-mct.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
17 down-counters and generate an interrupt when the counter expires. There is
23 - samsung,exynos4210-mct
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
12 (PLIC) high-level specification in the RISC-V Privileged Architecture
13 specification. The PLIC connects all external interrupts in the system to all
17 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
20 Each interrupt can be enabled on per-context basis. Any context can claim
[all …]
Dinterrupts.txt5 -------------------------
7 Nodes that describe devices which generate interrupts must contain an
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
13 which the interrupts are routed; see section 2 below for details.
16 interrupt-parent = <&intc1>;
17 interrupts = <5 0>, <6 0>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
[all …]
Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
16 Interrupts (LPI).
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
[all …]
/Linux-v5.10/arch/arm64/boot/dts/freescale/
Dfsl-ls1028a-kontron-sl28.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
9 /dts-v1/;
10 #include "fsl-ls1028a.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
16 model = "Kontron SMARC-sAL28";
29 compatible = "gpio-keys";
31 power-button {
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/gpio/
Dbrcm,brcmstb-gpio.txt3 The controller's registers are organized as sets of eight 32-bit
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
16 - #gpio-cells:
19 bit[0]: polarity (0 for active-high, 1 for active-low)
21 - gpio-controller:
24 - brcm,gpio-bank-widths:
30 - interrupts:
33 - interrupts-extended:
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/mfd/
Dkontron,sl28cpld.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Walle <michael@walle.cc>
26 "#address-cells":
29 "#size-cells":
32 "#interrupt-cells":
35 interrupts:
38 interrupt-controller: true
41 "^gpio(@[0-9a-f]+)?$":
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/serial/
Dmvebu-uart.txt2 e.g., Armada-3700.
5 - compatible:
6 - "marvell,armada-3700-uart" for the standard variant of the UART
7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
12 - reg: offset and length of the register set for the device.
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
18 - interrupts:
[all …]
/Linux-v5.10/include/linux/rtc/
Dds1685.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * DS1685/DS1687-series RTC chips.
8 * include larger, battery-backed NV-SRAM, burst-mode access, and an RTC
11 * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
12 * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
15 * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
16 * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
17 * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
18 * Application Note 90, Using the Multiplex Bus RTC Extended Features.
29 * struct ds1685_priv - DS1685 private data structure.
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/media/
Dsi4713.txt4 supporting 76-108 MHz. It includes an RDS encoder and has both, a stereo-analog
5 and a digital interface, which supports I2S, left-justified and a custom
6 DSP-mode format. It is programmable through an I2C interface.
9 - compatible: Should contain "silabs,si4713"
10 - reg: the I2C address of the device
13 - interrupts-extended: Interrupt specifier for the chips interrupt
14 - reset-gpios: GPIO specifier for the chips reset line
15 - vdd-supply: phandle for Vdd regulator
16 - vio-supply: phandle for Vio regulator
25 interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/remoteproc/
Dqcom,adsp.txt6 - compatible:
10 "qcom,msm8974-adsp-pil"
11 "qcom,msm8996-adsp-pil"
12 "qcom,msm8996-slpi-pil"
13 "qcom,msm8998-adsp-pas"
14 "qcom,msm8998-slpi-pas"
15 "qcom,qcs404-adsp-pas"
16 "qcom,qcs404-cdsp-pas"
17 "qcom,qcs404-wcss-pas"
18 "qcom,sc7180-mpss-pas"
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/power/supply/
Dqcom_smbb.txt1 Qualcomm Switch-Mode Battery Charger and Boost
4 - compatible:
8 - "qcom,pm8941-charger"
10 - reg:
12 Value type: <prop-encoded-array>
15 - interrupts:
17 Value type: <prop-encoded-array>
20 specifier for each of the following interrupts, in order:
21 - charge done
22 - charge fast mode
[all …]
Dbq24190.txt1 TI BQ24190 Li-Ion Battery Charger
4 - compatible: contains one of the following:
9 - reg: integer, I2C address of the charger.
10 - interrupts[-extended]: configuration for charger INT pin.
13 - monitored-battery: phandle of battery characteristics devicetree node
15 + precharge-current-microamp: maximum charge current during precharge
17 + charge-term-current-microamp: a charge cycle terminates when the
21 - ti,system-minimum-microvolt: when power is connected and the battery is below
25 - usb-otg-vbus:
31 - Some circuit boards wire the chip's "OTG" pin high (enabling 500mA default
[all …]
/Linux-v5.10/drivers/net/phy/
Dvitesse.c1 // SPDX-License-Identifier: GPL-2.0+
14 /* Vitesse Extended Page Magic Register(s) */
19 /* Vitesse Extended Control Register 1 */
55 /* Vitesse Extended Page Access Register */
58 /* Vitesse VSC8601 Extended PHY Control Register 1 */
108 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in vsc824x_config_init()
190 /* bits 14-15 in extended register 0x14 controls DACG amplitude in vsc738x_config_init()
191 * 6 = -8%, 2 is hardware default in vsc738x_config_init()
205 /* This magic sequence appears in the VSC7395 SparX-G5e application in vsc739x_config_init()
239 * with the power-on/reset defaults. Writing some registers will in vsc73xx_config_aneg()
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/input/touchscreen/
Dtsc2005.txt4 - compatible : "ti,tsc2004" or "ti,tsc2005"
5 - reg : Device address
6 - interrupts : IRQ specifier
7 - spi-max-frequency : Maximum SPI clocking speed of the device
11 - vio-supply : Regulator specifier
12 - reset-gpios : GPIO specifier for the controller reset line
13 - ti,x-plate-ohms : integer, resistance of the touchscreen's X plates
15 - ti,esd-recovery-timeout-ms : integer, if the touchscreen does not respond after
18 - properties defined in touchscreen.txt
26 vio-supply = <&vio>;
[all …]
/Linux-v5.10/arch/s390/include/asm/
Dcio.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 * struct ccw1 - channel command word
28 * operations with the device or the control unit. Only Format-1 channel
39 * struct ccw0 - channel command word
46 * The format-0 ccw structure.
80 * struct erw - extended report word
83 * @pvrf: path-verification-required flag
84 * @cpt: channel-path timeout
106 * struct erw_eadm - EADM Subchannel extended report word
118 * struct sublog - subchannel logout area
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/pinctrl/
Drenesas,pfc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
14 On SH/R-Mobile SoCs it also acts as a GPIO controller.
19 - renesas,pfc-emev2 # EMMA Mobile EV2
20 - renesas,pfc-r8a73a4 # R-Mobile APE6
21 - renesas,pfc-r8a7740 # R-Mobile A1
22 - renesas,pfc-r8a7742 # RZ/G1H
23 - renesas,pfc-r8a7743 # RZ/G1M
[all …]
/Linux-v5.10/arch/arm64/boot/dts/renesas/
Dr8a779a0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3U (R8A779A0) SoC
8 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779a0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a76";
[all …]

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