Lines Matching +full:interrupts +full:- +full:extended
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
37 compatible = "marvell,armada380-mbus", "simple-bus";
38 #address-cells = <2>;
39 #size-cells = <1>;
41 interrupt-parent = <&gic>;
42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
50 devbus_bootcs: devbus-bootcs {
51 compatible = "marvell,mvebu-devbus";
54 #address-cells = <1>;
55 #size-cells = <1>;
60 devbus_cs0: devbus-cs0 {
61 compatible = "marvell,mvebu-devbus";
64 #address-cells = <1>;
65 #size-cells = <1>;
70 devbus_cs1: devbus-cs1 {
71 compatible = "marvell,mvebu-devbus";
74 #address-cells = <1>;
75 #size-cells = <1>;
80 devbus_cs2: devbus-cs2 {
81 compatible = "marvell,mvebu-devbus";
84 #address-cells = <1>;
85 #size-cells = <1>;
90 devbus_cs3: devbus-cs3 {
91 compatible = "marvell,mvebu-devbus";
94 #address-cells = <1>;
95 #size-cells = <1>;
100 internal-regs {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
107 compatible = "marvell,armada-xp-sdram-controller";
111 L2: cache-controller@8000 {
112 compatible = "arm,pl310-cache";
114 cache-unified;
115 cache-level = <2>;
116 arm,double-linefill-incr = <0>;
117 arm,double-linefill-wrap = <0>;
118 arm,double-linefill = <0>;
119 prefetch-data = <1>;
123 compatible = "arm,cortex-a9-scu";
128 compatible = "arm,cortex-a9-global-timer";
130 interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
135 compatible = "arm,cortex-a9-twd-timer";
137 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
141 gic: interrupt-controller@d000 {
142 compatible = "arm,cortex-a9-gic";
143 #interrupt-cells = <3>;
144 #size-cells = <0>;
145 interrupt-controller;
151 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
153 #address-cells = <1>;
154 #size-cells = <0>;
155 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
161 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
163 #address-cells = <1>;
164 #size-cells = <0>;
165 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
171 compatible = "marvell,armada-38x-uart";
173 reg-shift = <2>;
174 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
175 reg-io-width = <1>;
181 compatible = "marvell,armada-38x-uart";
183 reg-shift = <2>;
184 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
185 reg-io-width = <1>;
193 ge0_rgmii_pins: ge-rgmii-pins-0 {
201 ge1_rgmii_pins: ge-rgmii-pins-1 {
209 i2c0_pins: i2c-pins-0 {
214 mdio_pins: mdio-pins {
219 ref_clk0_pins: ref-clk-pins-0 {
224 ref_clk1_pins: ref-clk-pins-1 {
229 spi0_pins: spi-pins-0 {
235 spi1_pins: spi-pins-1 {
241 nand_pins: nand-pins {
250 nand_rb: nand-rb {
255 uart0_pins: uart-pins-0 {
260 uart1_pins: uart-pins-1 {
265 sdhci_pins: sdhci-pins {
273 sata0_pins: sata-pins-0 {
278 sata1_pins: sata-pins-1 {
283 sata2_pins: sata-pins-2 {
288 sata3_pins: sata-pins-3 {
295 compatible = "marvell,armada-370-gpio",
296 "marvell,orion-gpio";
298 reg-names = "gpio", "pwm";
300 gpio-controller;
301 #gpio-cells = <2>;
302 #pwm-cells = <2>;
303 interrupt-controller;
304 #interrupt-cells = <2>;
305 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
313 compatible = "marvell,armada-370-gpio",
314 "marvell,orion-gpio";
316 reg-names = "gpio", "pwm";
318 gpio-controller;
319 #gpio-cells = <2>;
320 #pwm-cells = <2>;
321 interrupt-controller;
322 #interrupt-cells = <2>;
323 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
330 systemc: system-controller@18200 {
331 compatible = "marvell,armada-380-system-controller",
332 "marvell,armada-370-xp-system-controller";
336 gateclk: clock-gating-control@18220 {
337 compatible = "marvell,armada-380-gating-clock";
340 #clock-cells = <1>;
344 compatible = "marvell,armada-380-comphy";
345 reg-names = "comphy", "conf";
347 #address-cells = <1>;
348 #size-cells = <0>;
352 #phy-cells = <1>;
357 #phy-cells = <1>;
362 #phy-cells = <1>;
367 #phy-cells = <1>;
372 #phy-cells = <1>;
377 #phy-cells = <1>;
381 coreclk: mvebu-sar@18600 {
382 compatible = "marvell,armada-380-core-clock";
384 #clock-cells = <1>;
387 mbusc: mbus-controller@20000 {
388 compatible = "marvell,mbus-controller";
393 mpic: interrupt-controller@20a00 {
396 #interrupt-cells = <1>;
397 #size-cells = <1>;
398 interrupt-controller;
399 msi-controller;
400 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
404 compatible = "marvell,armada-380-timer",
405 "marvell,armada-xp-timer";
407 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
414 clock-names = "nbclk", "fixed";
418 compatible = "marvell,armada-380-wdt";
421 clock-names = "nbclk", "fixed";
422 interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
427 compatible = "marvell,armada-370-cpu-reset";
431 mpcore-soc-ctrl@20d20 {
432 compatible = "marvell,armada-380-mpcore-soc-ctrl";
436 coherencyfab: coherency-fabric@21010 {
437 compatible = "marvell,armada-380-coherency-fabric";
442 compatible = "marvell,armada-380-pmsu";
454 * from the one used in U-Boot and the
459 compatible = "marvell,armada-370-neta";
461 interrupts-extended = <&mpic 8>;
463 tx-csum-limit = <9800>;
468 compatible = "marvell,armada-370-neta";
470 interrupts-extended = <&mpic 10>;
476 compatible = "marvell,armada-370-neta";
478 interrupts-extended = <&mpic 12>;
484 compatible = "marvell,orion-ehci";
486 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
492 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
499 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
504 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
512 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
519 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
524 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
532 #address-cells = <1>;
533 #size-cells = <0>;
534 compatible = "marvell,orion-mdio";
540 compatible = "marvell,armada-38x-crypto";
542 reg-names = "regs";
543 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
547 clock-names = "cesa0", "cesa1",
549 marvell,crypto-srams = <&crypto_sram0>,
551 marvell,crypto-sram-size = <0x800>;
555 compatible = "marvell,armada-380-rtc";
557 reg-names = "rtc", "rtc-soc";
558 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
562 compatible = "marvell,armada-380-ahci";
564 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
570 compatible = "marvell,armada-380-neta-bm";
573 internal-mem = <&bm_bppi>;
578 compatible = "marvell,armada-380-ahci";
580 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
586 compatible = "marvell,armada-380-corediv-clock";
588 #clock-cells = <1>;
590 clock-output-names = "nand";
594 compatible = "marvell,armada380-thermal";
599 nand_controller: nand-controller@d0000 {
600 compatible = "marvell,armada370-nand-controller";
602 #address-cells = <1>;
603 #size-cells = <0>;
604 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
610 compatible = "marvell,armada-380-sdhci";
611 reg-names = "sdhci", "mbus", "conf-sdio3";
615 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
617 mrvl,clk-delay-cycles = <0x1F>;
622 compatible = "marvell,armada-380-xhci";
624 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
630 compatible = "marvell,armada-380-xhci";
632 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
638 crypto_sram0: sa-sram0 {
639 compatible = "mmio-sram";
642 #address-cells = <1>;
643 #size-cells = <1>;
647 crypto_sram1: sa-sram1 {
648 compatible = "mmio-sram";
651 #address-cells = <1>;
652 #size-cells = <1>;
656 bm_bppi: bm-bppi {
657 compatible = "mmio-sram";
660 #address-cells = <1>;
661 #size-cells = <1>;
663 no-memory-wc;
668 compatible = "marvell,armada-380-spi",
669 "marvell,orion-spi";
671 #address-cells = <1>;
672 #size-cells = <0>;
673 cell-index = <0>;
674 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
680 compatible = "marvell,armada-380-spi",
681 "marvell,orion-spi";
683 #address-cells = <1>;
684 #size-cells = <0>;
685 cell-index = <1>;
686 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
695 compatible = "fixed-clock";
696 #clock-cells = <0>;
697 clock-frequency = <1000000000>;
702 compatible = "fixed-clock";
703 #clock-cells = <0>;
704 clock-frequency = <25000000>;