Lines Matching +full:interrupts +full:- +full:extended
1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3U (R8A779A0) SoC
8 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779a0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a76";
25 power-domains = <&sysc R8A779A0_PD_A1E0D0C0>;
26 next-level-cache = <&L3_CA76_0>;
29 L3_CA76_0: cache-controller-0 {
31 power-domains = <&sysc R8A779A0_PD_A2E0D0>;
32 cache-unified;
33 cache-level = <3>;
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
41 clock-frequency = <0>;
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
48 clock-frequency = <0>;
52 compatible = "arm,cortex-a76-pmu";
53 interrupts-extended = <&gic GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
59 /* External SCIF clock - to be overridden by boards that provide it */
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 clock-frequency = <0>;
67 compatible = "simple-bus";
68 interrupt-parent = <&gic>;
69 #address-cells = <2>;
70 #size-cells = <2>;
73 cpg: clock-controller@e6150000 {
74 compatible = "renesas,r8a779a0-cpg-mssr";
77 clock-names = "extal", "extalr";
78 #clock-cells = <2>;
79 #power-domain-cells = <0>;
80 #reset-cells = <1>;
83 rst: reset-controller@e6160000 {
84 compatible = "renesas,r8a779a0-rst";
88 sysc: system-controller@e6180000 {
89 compatible = "renesas,r8a779a0-sysc";
91 #power-domain-cells = <1>;
95 compatible = "renesas,scif-r8a779a0",
96 "renesas,rcar-gen3-scif", "renesas,scif";
98 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
102 clock-names = "fck", "brg_int", "scif_clk";
103 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
108 gic: interrupt-controller@f1000000 {
109 compatible = "arm,gic-v3";
110 #interrupt-cells = <3>;
111 #address-cells = <0>;
112 interrupt-controller;
115 interrupts = <GIC_PPI 9
117 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
127 compatible = "arm,armv8-timer";
128 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,